34 lines
1.2 KiB
Python
34 lines
1.2 KiB
Python
from ..base import CpuifBase
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class APB4_Cpuif(CpuifBase):
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template_path = "cpuif/apb4/apb4_tmpl.sv"
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@property
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def port_declaration(self) -> str:
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return "apb4_intf.slave s_apb"
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def signal(self, name:str) -> str:
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return "s_apb." + name
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class APB4_Cpuif_flattened(APB4_Cpuif):
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@property
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def port_declaration(self) -> str:
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# TODO: Reference data/addr width from verilog parameter perhaps?
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lines = [
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"input wire " + self.signal("psel"),
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"input wire " + self.signal("penable"),
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"input wire " + self.signal("pwrite"),
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"input wire " + self.signal("pprot"),
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f"input wire [{self.addr_width-1}:0] " + self.signal("paddr"),
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f"input wire [{self.data_width-1}:0] " + self.signal("pwdata"),
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f"input wire [{(self.data_width / 8)-1}:0] " + self.signal("pstrb"),
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"output logic " + self.signal("pready"),
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f"output logic [{self.data_width-1}:0] " + self.signal("prdata"),
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"output logic " + self.signal("pslverr"),
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]
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return ",\n".join(lines)
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def signal(self, name:str) -> str:
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return "s_apb_" + name
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