17 lines
520 B
Systemverilog
17 lines
520 B
Systemverilog
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/*
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* Creates an always_ff begin/end block with the appropriate edge sensitivity
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* list depending on the resetsignal used
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*/
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{% macro AlwaysFF(resetsignal) %}
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{%- if resetsignal.is_async and resetsignal.is_activehigh %}
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always_ff @(posedge clk or posedge {{resetsignal.identifier}}) begin
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{%- elif resetsignal.is_async and not resetsignal.is_activehigh %}
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always_ff @(posedge clk or negedge {{resetsignal.identifier}}) begin
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{%- else %}
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always_ff @(posedge clk) begin
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{%- endif %}
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{{- caller() }}
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end
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{%- endmacro %}
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