d69af23be5
* feat: add ability to enable error output on the cpuif, when decoding errors occur (generate_cpuif_err in API). * fix: move signal to new place (after automatic vers) * feat: add info about new api (generate_cpuif_err) * fix: repair readback with latency * Adding generate_cpuif_err argument to peakrdl-regblock to generate cpuif error response, when the address is decoded incorrectly * add sw rd or/and wr attribure error response related and add error respone for external mem * add sw rd or/and wr error response test * add sw rd or/and wr error response for external register test and fix generation of rtl logic for external register * add sw rd or/and wr error response for external mem test * add sw rd or/and wr error response for apb3 imterfaces driver * add error response test for APB4, AXI4Lite and Avalon interfaces * rename --generate_cpuif_err to --generate-cpuif-err * style: minor typo fixes and test clean-up * refactor: move expected error check inside write/read functions * feat: add error response check to OBI testbench interface * feat: split generate-cpuif-err option into err-if-bad-addr and err-if-bad-rw options * feat: add err_if_bad_addr/rw to cfg_schema * feat: extend cpuif_err_rsp test to cover all combinations of bad_addr/bad_rw * style: lint fixes * fix: removed redundant if node.external condition to help coverage * Fix dangling hwif_in signals in testcase --------- Co-authored-by: Denis Trifonov <d.trifonov@yadro.com> Co-authored-by: Dominik Tanous <tanous@kandou.com> Co-authored-by: Sebastien Baillou <baillou@kandou.com> Co-authored-by: Alex Mykyta <amykyta3@users.noreply.github.com>
222 lines
6.4 KiB
Systemverilog
222 lines
6.4 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{%- block dut_support %}
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{% sv_line_anchor %}
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external_reg ext_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.er_rw.req),
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.req_is_wr(hwif_out.er_rw.req_is_wr),
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.wr_data(hwif_out.er_rw.wr_data),
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.wr_biten(hwif_out.er_rw.wr_biten),
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.rd_ack(hwif_in.er_rw.rd_ack),
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.rd_data(hwif_in.er_rw.rd_data),
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.wr_ack(hwif_in.er_rw.wr_ack)
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);
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external_reg ro_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.er_r.req),
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.req_is_wr(hwif_out.er_r.req_is_wr),
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.wr_data(32'b0),
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.wr_biten(32'b0),
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.rd_ack(hwif_in.er_r.rd_ack),
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.rd_data(hwif_in.er_r.rd_data),
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.wr_ack()
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);
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external_reg wo_reg_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.er_w.req),
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.req_is_wr(hwif_out.er_w.req_is_wr),
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.wr_data(hwif_out.er_w.wr_data),
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.wr_biten(hwif_out.er_w.wr_biten),
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.rd_ack(),
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.rd_data(),
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.wr_ack(hwif_in.er_w.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(3)
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) mem_rw_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mem_rw.req),
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.req_is_wr(hwif_out.mem_rw.req_is_wr),
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.addr(hwif_out.mem_rw.addr),
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.wr_data(hwif_out.mem_rw.wr_data),
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.wr_biten(hwif_out.mem_rw.wr_biten),
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.rd_ack(hwif_in.mem_rw.rd_ack),
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.rd_data(hwif_in.mem_rw.rd_data),
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.wr_ack(hwif_in.mem_rw.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(3)
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) mem_ro_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mem_r.req),
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.req_is_wr(hwif_out.mem_r.req_is_wr),
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.addr(hwif_out.mem_r.addr),
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.wr_data(32'b0),
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.wr_biten(32'b0),
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.rd_ack(hwif_in.mem_r.rd_ack),
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.rd_data(hwif_in.mem_r.rd_data),
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.wr_ack(hwif_in.mem_r.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(3)
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) mem_wo_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mem_w.req),
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.req_is_wr(hwif_out.mem_w.req_is_wr),
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.addr(hwif_out.mem_w.addr),
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.wr_data(hwif_out.mem_w.wr_data),
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.wr_biten(hwif_out.mem_w.wr_biten),
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.rd_ack(),
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.rd_data(),
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.wr_ack(hwif_in.mem_w.wr_ack)
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);
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assign hwif_in.mem_w.rd_ack = '0;
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assign hwif_in.mem_w.rd_data = '0;
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{%- endblock %}
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{% block seq %}
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logic wr_err;
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logic expected_wr_err;
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logic expected_rd_err;
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logic bad_addr_expected_err;
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logic bad_rw_expected_wr_err;
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logic bad_rw_expected_rd_err;
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logic [5:0] addr;
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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{%- if testcase.err_if_bad_addr %}
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bad_addr_expected_err = 1'b1;
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{%- else %}
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bad_addr_expected_err = 1'b0;
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{%- endif %}
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{%- if testcase.err_if_bad_rw %}
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bad_rw_expected_wr_err = 1'b1;
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bad_rw_expected_rd_err = 1'b1;
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{%- else %}
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bad_rw_expected_wr_err = 1'b0;
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bad_rw_expected_rd_err = 1'b0;
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{%- endif %}
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// r_rw - sw=rw; hw=na; // Storage element
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addr = 'h0;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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cpuif.assert_read(addr, 40, .expects_err(expected_rd_err));
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cpuif.write('h0, 61, .expects_err(expected_wr_err));
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cpuif.assert_read('h0, 61, .expects_err(expected_rd_err));
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// r_r - sw=r; hw=na; // Wire/Bus - constant value
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addr = 'h4;
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expected_rd_err = 'h0;
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expected_wr_err = bad_rw_expected_wr_err;
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cpuif.assert_read(addr, 80, .expects_err(expected_rd_err));
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cpuif.write(addr, 81, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 80, .expects_err(expected_rd_err));
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// r_w - sw=w; hw=r; // Storage element
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addr = 'h8;
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expected_rd_err = bad_rw_expected_rd_err;
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expected_wr_err = 'h0;
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(cb.hwif_out.r_w.f.value == 100);
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cpuif.write(addr, 101, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(cb.hwif_out.r_w.f.value == 101);
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// External registers
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// er_rw - sw=rw; hw=na; // Storage element
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addr = 'hC;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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ext_reg_inst.value = 'h8C;
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cpuif.assert_read(addr, 'h8C, .expects_err(expected_rd_err));
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cpuif.write(addr, 'h8D, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'h8D, .expects_err(expected_rd_err));
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// er_r - sw=r; hw=na; // Wire/Bus - constant value
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addr = 'h10;
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expected_rd_err = 'h0;
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expected_wr_err = bad_rw_expected_wr_err;
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ro_reg_inst.value = 'hB4;
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cpuif.assert_read(addr, 'hB4, .expects_err(expected_rd_err));
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cpuif.write(addr, 'hB5, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'hB4, .expects_err(expected_rd_err));
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// er_w - sw=w; hw=r; // Storage element
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addr = 'h14;
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expected_rd_err = bad_rw_expected_rd_err;
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expected_wr_err = 'h0;
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wo_reg_inst.value = 'hC8;
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(wo_reg_inst.value == 'hC8);
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cpuif.write(addr, 'hC9, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(wo_reg_inst.value == 'hC9);
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// Reading/writing from/to non existing register
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addr = 'h18;
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cpuif.assert_read(addr, 0, .expects_err(bad_addr_expected_err));
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cpuif.write(addr, 'h8C, .expects_err(bad_addr_expected_err));
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// External memories
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// mem_rw - sw=rw;
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addr = 'h20;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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mem_rw_inst.mem[0] = 'h8C;
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cpuif.assert_read(addr, 'h8C, .expects_err(expected_rd_err));
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cpuif.write(addr, 'h8D, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'h8D, .expects_err(expected_rd_err));
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// mem_r - sw=r;
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addr = 'h28;
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expected_rd_err = 'h0;
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expected_wr_err = bad_rw_expected_wr_err;
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mem_ro_inst.mem[0] = 'hB4;
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cpuif.assert_read(addr, 'hB4, .expects_err(expected_rd_err));
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cpuif.write(addr, 'hB5, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'hB4, .expects_err(expected_rd_err));
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// mem_w - sw=w;
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addr = 'h30;
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expected_rd_err = bad_rw_expected_rd_err;
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expected_wr_err = 'h0;
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mem_wo_inst.mem[0] = 'hC8;
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(mem_wo_inst.mem[0] == 'hC8);
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cpuif.write(addr, 'hC9, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(mem_wo_inst.mem[0] == 'hC9);
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{% endblock %}
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