15 lines
531 B
Systemverilog
15 lines
531 B
Systemverilog
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
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// https://github.com/SystemRDL/PeakRDL-regblock
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package {{ds.package_name}};
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localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
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localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
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localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};
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{{-hwif.get_extra_package_params()|indent}}
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{{-hwif.get_package_contents()|indent}}
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endpackage
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{# (eof newline anchor) #}
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