bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
148 Commits 1 Branch 0 Tags
639cafc28b64f9df592e90cb5e3638716880ee0f
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Alex Mykyta 639cafc28b Fix always_ff generation for non-reset fields and async default reset. #63
2023-09-07 23:36:47 -07:00
.github/workflows
Add coveralls
2023-03-13 21:47:33 -07:00
docs
Doc updates
2023-08-03 22:53:22 -07:00
hdl-src
Add Intel Avalon MM cpuif. #40
2023-05-14 17:00:55 -07:00
src/peakrdl_regblock
Fix always_ff generation for non-reset fields and async default reset. #63
2023-09-07 23:36:47 -07:00
tests
Fix xsim compatibility quirk
2023-09-07 23:16:58 -07:00
.gitignore
Add support for field paritycheck. #35
2023-05-15 22:53:17 -07:00
LICENSE
initial dev
2021-06-01 21:57:12 -07:00
MANIFEST.in
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
README.md
Add coveralls
2023-03-13 21:47:33 -07:00
setup.py
Add changelog
2023-07-19 21:09:20 -07:00

README.md

Documentation Status build Coverage Status PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

Reference in New Issue View Git Blame Copy Permalink
Description
No description provided
Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%