bslathi19/PeakRDL-regblock
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Alex Mykyta 693040d145 Fix doc search path
2022-05-27 23:11:55 -07:00
.github/workflows
Enable Vivado's xsim to run on some simpler testcases for better compile-check coverage. #7
2022-05-02 20:22:55 -07:00
docs
Fix doc search path
2022-05-27 23:11:55 -07:00
src/peakrdl/regblock
bump version
2022-05-17 22:08:39 -07:00
tests
tweak readme
2022-05-02 21:01:16 -07:00
.gitignore
Improve template path handling. Add synthesis tests
2022-02-23 22:53:54 -08:00
LICENSE
initial dev
2021-06-01 21:57:12 -07:00
MANIFEST.in
Reorganize test dir to ensure test of installed pkg
2022-02-28 23:08:41 -08:00
README.md
doc tweaks
2022-02-28 22:10:09 -08:00
setup.py
Reorganize test dir to ensure test of installed pkg
2022-02-28 23:08:41 -08:00

README.md

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%