bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
87 Commits 1 Branch 0 Tags
71c53b14e179223415d6c2b9d930d1f21d3092d8
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Alex Mykyta 71c53b14e1 phrasing
2022-11-09 23:18:47 -08:00
.github/workflows
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
docs
phrasing
2022-11-09 23:18:47 -08:00
hdl-src
Add 'rd_swacc' and 'wr_swacc' UDPs. #21
2022-11-09 21:25:02 -08:00
src/peakrdl_regblock
Add 'rd_swacc' and 'wr_swacc' UDPs. #21
2022-11-09 21:25:02 -08:00
tests
Add 'rd_swacc' and 'wr_swacc' UDPs. #21
2022-11-09 21:25:02 -08:00
.gitignore
Improve template path handling. Add synthesis tests
2022-02-23 22:53:54 -08:00
LICENSE
initial dev
2021-06-01 21:57:12 -07:00
MANIFEST.in
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
README.md
Update readme
2022-07-30 23:05:21 -07:00
setup.py
Implement write buffering (#22)
2022-10-29 22:02:04 -07:00

README.md

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

Reference in New Issue View Git Blame Copy Permalink
Description
No description provided
Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%