331 lines
13 KiB
Python
331 lines
13 KiB
Python
from typing import TYPE_CHECKING
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from systemrdl.rdltypes import PropertyReference, PrecedenceType, InterruptType
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from systemrdl.node import Node
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from .bases import AssignmentPrecedence, NextStateConditional
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from . import sw_onread
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from . import sw_onwrite
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from . import sw_singlepulse
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from . import hw_write
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from . import hw_set_clr
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from . import hw_interrupts
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from ..utils import get_indexed_path
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from .generators import CombinationalStructGenerator, FieldStorageStructGenerator, FieldLogicGenerator
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if TYPE_CHECKING:
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from typing import Dict, List
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from systemrdl.node import AddrmapNode, FieldNode
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from ..exporter import RegblockExporter
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class FieldLogic:
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def __init__(self, exp:'RegblockExporter'):
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self.exp = exp
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self._hw_conditionals = {} # type: Dict[int, List[NextStateConditional]]
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self._sw_conditionals = {} # type: Dict[int, List[NextStateConditional]]
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self.init_conditionals()
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@property
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def top_node(self) -> 'AddrmapNode':
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return self.exp.top_node
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def get_storage_struct(self) -> str:
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struct_gen = FieldStorageStructGenerator(self)
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s = struct_gen.get_struct(self.top_node, "field_storage_t")
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# Only declare the storage struct if it exists
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if s is None:
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return ""
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return s + "\nfield_storage_t field_storage;"
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def get_combo_struct(self) -> str:
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struct_gen = CombinationalStructGenerator(self)
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s = struct_gen.get_struct(self.top_node, "field_combo_t")
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# Only declare the storage struct if it exists
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if s is None:
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return ""
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return s + "\nfield_combo_t field_combo;"
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def get_implementation(self) -> str:
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gen = FieldLogicGenerator(self)
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s = gen.get_content(self.top_node)
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if s is None:
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return ""
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return s
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#---------------------------------------------------------------------------
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# Field utility functions
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#---------------------------------------------------------------------------
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def get_storage_identifier(self, field: 'FieldNode') -> str:
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"""
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Returns the Verilog string that represents the storage register element
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for the referenced field
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"""
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assert field.implements_storage
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path = get_indexed_path(self.top_node, field)
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return f"field_storage.{path}.value"
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def get_next_q_identifier(self, field: 'FieldNode') -> str:
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"""
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Returns the Verilog string that represents the storage register element
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for the delayed 'next' input value
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"""
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assert field.implements_storage
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path = get_indexed_path(self.top_node, field)
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return f"field_storage.{path}.next_q"
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def get_field_combo_identifier(self, field: 'FieldNode', name: str) -> str:
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"""
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Returns a Verilog string that represents a field's internal combinational
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signal.
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"""
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assert field.implements_storage
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path = get_indexed_path(self.top_node, field)
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return f"field_combo.{path}.{name}"
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def get_counter_incr_strobe(self, field: 'FieldNode') -> str:
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"""
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Return the Verilog string that represents the field's incr strobe signal.
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"""
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prop_value = field.get_property('incr')
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if prop_value:
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return self.exp.dereferencer.get_value(prop_value)
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# unset by the user, points to the implied input signal
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return self.exp.hwif.get_implied_prop_input_identifier(field, "incr")
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def get_counter_incrvalue(self, field: 'FieldNode') -> str:
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"""
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Return the string that represents the field's increment value
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"""
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incrvalue = field.get_property('incrvalue')
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if incrvalue is not None:
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return self.exp.dereferencer.get_value(incrvalue)
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if field.get_property('incrwidth'):
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return self.exp.hwif.get_implied_prop_input_identifier(field, "incrvalue")
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return "1'b1"
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def get_counter_incrsaturate_value(self, field: 'FieldNode') -> str:
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prop_value = field.get_property('incrsaturate')
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if prop_value is True:
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return self.exp.dereferencer.get_value(2**field.width - 1)
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return self.exp.dereferencer.get_value(prop_value)
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def counter_incrsaturates(self, field: 'FieldNode') -> bool:
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"""
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Returns True if the counter saturates
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"""
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return field.get_property('incrsaturate') is not False
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def get_counter_incrthreshold_value(self, field: 'FieldNode') -> str:
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prop_value = field.get_property('incrthreshold')
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if isinstance(prop_value, bool):
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# No explicit value set. use max
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return self.exp.dereferencer.get_value(2**field.width - 1)
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return self.exp.dereferencer.get_value(prop_value)
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def get_counter_decr_strobe(self, field: 'FieldNode') -> str:
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"""
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Return the Verilog string that represents the field's incr strobe signal.
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"""
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prop_value = field.get_property('decr')
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if prop_value:
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return self.exp.dereferencer.get_value(prop_value)
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# unset by the user, points to the implied input signal
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return self.exp.hwif.get_implied_prop_input_identifier(field, "decr")
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def get_counter_decrvalue(self, field: 'FieldNode') -> str:
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"""
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Return the string that represents the field's decrement value
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"""
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decrvalue = field.get_property('decrvalue')
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if decrvalue is not None:
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return self.exp.dereferencer.get_value(decrvalue)
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if field.get_property('decrwidth'):
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return self.exp.hwif.get_implied_prop_input_identifier(field, "decrvalue")
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return "1'b1"
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def get_counter_decrsaturate_value(self, field: 'FieldNode') -> str:
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prop_value = field.get_property('decrsaturate')
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if prop_value is True:
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return "'d0"
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return self.exp.dereferencer.get_value(prop_value)
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def counter_decrsaturates(self, field: 'FieldNode') -> bool:
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"""
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Returns True if the counter saturates
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"""
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return field.get_property('decrsaturate') is not False
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def get_counter_decrthreshold_value(self, field: 'FieldNode') -> str:
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prop_value = field.get_property('decrthreshold')
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if isinstance(prop_value, bool):
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# No explicit value set. use min
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return "'d0"
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return self.exp.dereferencer.get_value(prop_value)
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def get_swacc_identifier(self, field: 'FieldNode') -> str:
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"""
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Asserted when field is software accessed (read)
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"""
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strb = self.exp.dereferencer.get_access_strobe(field)
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return f"{strb} && !decoded_req_is_wr"
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def get_swmod_identifier(self, field: 'FieldNode') -> str:
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"""
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Asserted when field is modified by software (written or read with a
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set or clear side effect).
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"""
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w_modifiable = field.is_sw_writable
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r_modifiable = (field.get_property('onread') is not None)
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strb = self.exp.dereferencer.get_access_strobe(field)
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if w_modifiable and not r_modifiable:
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# assert swmod only on sw write
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return f"{strb} && decoded_req_is_wr"
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if w_modifiable and r_modifiable:
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# assert swmod on all sw actions
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return strb
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if not w_modifiable and r_modifiable:
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# assert swmod only on sw read
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return f"{strb} && !decoded_req_is_wr"
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# Not sw modifiable
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return "1'b0"
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def has_next_q(self, field: 'FieldNode') -> bool:
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"""
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Some fields require a delayed version of their 'next' input signal in
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order to do edge-detection.
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Returns True if this is the case.
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"""
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if field.get_property('intr type') in {
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InterruptType.posedge,
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InterruptType.negedge,
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InterruptType.bothedge
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}:
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return True
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return False
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#---------------------------------------------------------------------------
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# Field Logic Conditionals
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#---------------------------------------------------------------------------
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def add_hw_conditional(self, conditional: NextStateConditional, precedence: AssignmentPrecedence) -> None:
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"""
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Register a NextStateConditional action for hardware-triggered field updates.
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Categorizing conditionals correctly by hw/sw ensures that the RDL precedence
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property can be reliably honored.
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The ``precedence`` argument determines the conditional assignment's priority over
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other assignments of differing precedence.
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If multiple conditionals of the same precedence are registered, they are
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searched sequentially and only the first to match the given field is used.
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"""
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if precedence not in self._hw_conditionals:
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self._hw_conditionals[precedence] = []
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self._hw_conditionals[precedence].append(conditional)
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def add_sw_conditional(self, conditional: NextStateConditional, precedence: AssignmentPrecedence) -> None:
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"""
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Register a NextStateConditional action for software-triggered field updates.
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Categorizing conditionals correctly by hw/sw ensures that the RDL precedence
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property can be reliably honored.
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The ``precedence`` argument determines the conditional assignment's priority over
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other assignments of differing precedence.
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If multiple conditionals of the same precedence are registered, they are
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searched sequentially and only the first to match the given field is used.
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"""
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if precedence not in self._sw_conditionals:
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self._sw_conditionals[precedence] = []
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self._sw_conditionals[precedence].append(conditional)
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def init_conditionals(self) -> None:
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"""
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Initialize all possible conditionals here.
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Remember: The order in which conditionals are added matters within the
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same assignment precedence.
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"""
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self.add_sw_conditional(sw_onread.ClearOnRead(self.exp), AssignmentPrecedence.SW_ONREAD)
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self.add_sw_conditional(sw_onread.SetOnRead(self.exp), AssignmentPrecedence.SW_ONREAD)
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self.add_sw_conditional(sw_onwrite.Write(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteSet(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteClear(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteZeroToggle(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteZeroClear(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteZeroSet(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteOneToggle(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteOneClear(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_onwrite.WriteOneSet(self.exp), AssignmentPrecedence.SW_ONWRITE)
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self.add_sw_conditional(sw_singlepulse.Singlepulse(self.exp), AssignmentPrecedence.SW_SINGLEPULSE)
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self.add_hw_conditional(hw_interrupts.PosedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.NegedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.BothedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.PosedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.NegedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.BothedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.Sticky(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_interrupts.Stickybit(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_write.WEWrite(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_write.WELWrite(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_write.AlwaysWrite(self.exp), AssignmentPrecedence.HW_WRITE)
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self.add_hw_conditional(hw_set_clr.HWClear(self.exp), AssignmentPrecedence.HWCLR)
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self.add_hw_conditional(hw_set_clr.HWSet(self.exp), AssignmentPrecedence.HWSET)
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def _get_X_conditionals(self, conditionals: 'Dict[int, List[NextStateConditional]]', field: 'FieldNode') -> 'List[NextStateConditional]':
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result = []
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precedences = sorted(conditionals.keys(), reverse=True)
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for precedence in precedences:
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for conditional in conditionals[precedence]:
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if conditional.is_match(field):
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result.append(conditional)
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break
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return result
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def get_conditionals(self, field: 'FieldNode') -> 'List[NextStateConditional]':
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"""
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Get a list of NextStateConditional objects that apply to the given field.
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The returned list is sorted in priority order - the conditional with highest
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precedence is first in the list.
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"""
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sw_precedence = (field.get_property('precedence') == PrecedenceType.sw)
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result = []
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if sw_precedence:
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result.extend(self._get_X_conditionals(self._sw_conditionals, field))
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result.extend(self._get_X_conditionals(self._hw_conditionals, field))
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if not sw_precedence:
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result.extend(self._get_X_conditionals(self._sw_conditionals, field))
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return result
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