100 lines
2.8 KiB
Systemverilog
100 lines
2.8 KiB
Systemverilog
{% sv_line_anchor %}
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module tb;
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timeunit 1ns;
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timeprecision 1ps;
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logic rst = '1;
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logic clk = '0;
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initial forever begin
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#5ns;
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clk = ~clk;
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end
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//--------------------------------------------------------------------------
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// DUT Signal declarations
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//--------------------------------------------------------------------------
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{%- if exporter.hwif.has_input_struct %}
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regblock_pkg::regblock__in_t hwif_in;
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{%- endif %}
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{%- if exporter.hwif.has_output_struct %}
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regblock_pkg::regblock__out_t hwif_out;
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{%- endif %}
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{%- block declarations %}
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{%- endblock %}
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//--------------------------------------------------------------------------
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// Clocking
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//--------------------------------------------------------------------------
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default clocking cb @(posedge clk);
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default input #1step output #1;
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output rst;
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{%- if exporter.hwif.has_input_struct %}
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output hwif_in;
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{%- endif %}
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{%- if exporter.hwif.has_output_struct %}
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input hwif_out;
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{%- endif %}
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{%- filter indent %}
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{%- block clocking_dirs %}
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{%- endblock %}
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{%- endfilter %}
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endclocking
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//--------------------------------------------------------------------------
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// CPUIF
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//--------------------------------------------------------------------------
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{{cls.cpuif.get_tb_inst(cls, exporter)|indent}}
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//--------------------------------------------------------------------------
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// DUT
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//--------------------------------------------------------------------------
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{% sv_line_anchor %}
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regblock dut (.*);
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{%- if exporter.hwif.has_output_struct %}
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{% sv_line_anchor %}
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initial begin
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logic [$bits(hwif_out)-1:0] tmp;
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forever begin
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##1;
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tmp = {>>{hwif_out}}; // Workaround for Xilinx's xsim - assign to tmp variable
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if(!rst) assert(!$isunknown(tmp)) else $error("hwif_out has X's!");
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end
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end
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{%- endif %}
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{% sv_line_anchor %}
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//--------------------------------------------------------------------------
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// Test Sequence
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//--------------------------------------------------------------------------
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initial begin
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cb.rst <= '1;
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{%- if exporter.hwif.has_input_struct %}
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cb.hwif_in <= '{default: '0};
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{%- endif %}
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begin
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{%- filter indent(8) %}
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{%- block seq %}
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{%- endblock %}
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{%- endfilter %}
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end
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{% sv_line_anchor %}
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##5;
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$finish();
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end
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//--------------------------------------------------------------------------
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// Monitor for timeout
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//--------------------------------------------------------------------------
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initial begin
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##{{cls.timeout_clk_cycles}};
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$fatal(1, "Test timed out after {{cls.timeout_clk_cycles}} clock cycles");
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end
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endmodule
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