33 lines
1.3 KiB
Systemverilog
33 lines
1.3 KiB
Systemverilog
{%- import 'field_logic/templates/counter_macros.sv' as counter_macros with context -%}
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// Field: {{node.get_path()}}
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always_comb begin
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automatic logic [{{node.width-1}}:0] next_c = field_storage.{{field_path}};
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automatic logic load_next_c = '0;
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{%- for signal in extra_combo_signals %}
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field_combo.{{field_path}}.{{signal.name}} = {{signal.default_assignment}};
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{%- endfor %}
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{% for conditional in conditionals %}
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{%- if not loop.first %} else {% endif %}if({{conditional.get_predicate(node)}}) begin // {{conditional.comment}}
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{%- for assignment in conditional.get_assignments(node) %}
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{{assignment|indent}}
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{%- endfor %}
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end
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{%- endfor %}
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{%- if node.is_up_counter %}
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{{counter_macros.up_counter(node)}}
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{%- endif %}
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{%- if node.is_down_counter %}
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{{counter_macros.down_counter(node)}}
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{%- endif %}
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field_combo.{{field_path}}.next = next_c;
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field_combo.{{field_path}}.load_next = load_next_c;
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end
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always_ff {{get_always_ff_event(resetsignal)}} begin
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{% if resetsignal is not none -%}
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if({{resetsignal.activehigh_identifier}}) begin
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field_storage.{{field_path}} <= {{reset}};
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end else {% endif %}if(field_combo.{{field_path}}.load_next) begin
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field_storage.{{field_path}} <= field_combo.{{field_path}}.next;
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end
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end
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