92 lines
2.3 KiB
Python
92 lines
2.3 KiB
Python
from typing import TYPE_CHECKING
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if TYPE_CHECKING:
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from systemrdl import SignalNode
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class SignalBase:
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@property
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def is_async(self) -> bool:
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raise NotImplementedError()
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@property
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def is_activehigh(self) -> bool:
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raise NotImplementedError()
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@property
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def width(self) -> int:
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raise NotImplementedError()
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@property
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def identifier(self) -> str:
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raise NotImplementedError()
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@property
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def activehigh_identifier(self) -> str:
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"""
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Normalizes the identifier reference to be active-high logic
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"""
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if not self.is_activehigh:
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return "~%s" % self.identifier
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return self.identifier
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@property
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def port_declaration(self) -> str:
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"""
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Returns the port delcaration text for this signal.
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In the context of this exporter, all signal objects happen to be inputs.
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"""
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if self.width > 1:
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return "input wire [%d:0] %s" % (self.width - 1, self.identifier)
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return "input wire %s" % self.identifier
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class RDLSignal(SignalBase):
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"""
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Wrapper around a SystemRDL signal object
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"""
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def __init__(self, rdl_signal:'SignalNode'):
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self.rdl_signal = rdl_signal
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@property
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def is_async(self) -> bool:
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return self.rdl_signal.get_property('async')
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@property
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def is_activehigh(self) -> bool:
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return self.rdl_signal.get_property('activehigh')
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@property
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def width(self) -> int:
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return self.rdl_signal.width
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@property
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def identifier(self) -> str:
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# TODO: uniquify this somehow
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# TODO: Deal with different hierarchies
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return "TODO_%s" % self.rdl_signal.inst_name
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class InferredSignal(SignalBase):
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def __init__(self, identifier:str, width:int=1, is_async:bool=False, is_activehigh=True):
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self._identifier = identifier
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self._width = width
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self._is_async = is_async
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self._is_activehigh = is_activehigh
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@property
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def is_async(self) -> bool:
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return self._is_async
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@property
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def is_activehigh(self) -> bool:
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return self._is_activehigh
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@property
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def width(self) -> int:
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return self._width
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@property
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def identifier(self) -> str:
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return self._identifier
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