35 lines
753 B
Systemverilog
35 lines
753 B
Systemverilog
{% extends "lib/tb_base.sv" %}
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{%- block declarations %}
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{% sv_line_anchor %}
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localparam REGWIDTH = {{cls.regwidth}};
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localparam STRIDE = REGWIDTH/8;
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localparam N_REGS = {{cls.n_regs}};
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{%- endblock %}
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{% block seq %}
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{% sv_line_anchor %}
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bit [REGWIDTH-1:0] data[N_REGS];
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##1;
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cb.rst <= '0;
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##1;
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foreach(data[i]) data[i] = {$urandom(), $urandom(), $urandom(), $urandom()};
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for(int i=0; i<N_REGS; i++) begin
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cpuif.assert_read(i*STRIDE, 'h1);
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end
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for(int i=0; i<N_REGS; i++) begin
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cpuif.write(i*STRIDE, data[i]);
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end
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for(int i=0; i<N_REGS; i++) begin
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cpuif.assert_read(i*STRIDE, data[i]);
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end
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assert($bits(dut.cpuif_wr_data) == REGWIDTH);
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{% endblock %}
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