Alex Mykyta 833c515cd2 Re-enable xsim for testcases. Works better in Vivado 2024.2

2025-04-11 22:19:19 -07:00

..

__init__.py

Add support for wide registers (where accesswidth < regwidth)

2022-10-17 22:13:29 -07:00

regblock.rdl

Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

2023-10-24 22:50:41 -07:00

tb_template.sv

Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

2023-10-24 22:50:41 -07:00

testcase.py

Re-enable xsim for testcases. Works better in Vivado 2024.2

2025-04-11 22:19:19 -07:00