50 lines
1.4 KiB
Python
50 lines
1.4 KiB
Python
import os
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from parameterized import parameterized_class
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from ..lib.sim_testcase import SimTestCase
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from ..lib.synth_testcase import SynthTestCase
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from ..lib.test_params import TEST_PARAMS, get_permutations
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from ..lib.simulators.xilinx import Xilinx
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import pytest
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@parameterized_class(TEST_PARAMS)
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class TestParameterizations(SimTestCase):
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def test_dut(self):
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self.run_test()
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@parameterized_class(get_permutations({
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"default_reset_activelow": [True, False],
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"default_reset_async": [True, False],
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}))
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class TestDefaultResets(SimTestCase):
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def test_dut(self):
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self.run_test()
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@parameterized_class(TEST_PARAMS)
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class TestSynth(SynthTestCase):
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def test_dut(self):
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self.run_synth()
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@pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False) or os.environ.get("NO_XSIM", False), reason="user skipped")
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@parameterized_class(TEST_PARAMS)
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class TestVivado(SimTestCase):
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"""
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Vivado XSIM's implementation of clocking blocks is broken, which is heavily used
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by the testbench infrastructure in most testcases.
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Since this group of tests does not rely on writing HWIF values, the bugs in
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xsim are avoided.
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Run this testcase using xsim to get some cross-simulator coverage.
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Goal is to validate the generated RTL doesn't use constructs that offend xsim.
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This is skipped in CI stub tests as it doesn't add value
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"""
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simulator_cls = Xilinx
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def test_dut(self):
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self.run_test()
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