Alex Mykyta 54ac56e1c3 Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

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cpuifs

Simulator compatibility updates

2023-10-22 20:43:34 -07:00

simulators

Fix incorrect bit-order in packed struct output of external registers. #111

2024-12-18 21:17:31 -08:00

synthesizers

Reorganize how tb infrstructure selects toolchains

2023-10-22 11:04:43 -07:00

__init__.py

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base_testcase.py

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

external_block.sv

Simulator compatibility updates

2023-10-22 20:43:34 -07:00

external_reg.sv

Simulator compatibility updates

2023-10-22 20:43:34 -07:00

sim_testcase.py

Simulator compatibility updates

2023-10-22 20:43:34 -07:00

sv_line_anchor.py

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synth_testcase.py

Reorganize how tb infrstructure selects toolchains

2023-10-22 11:04:43 -07:00

tb_base.sv

Fixup test bitswap. mypy

2024-12-18 22:04:12 -08:00

test_params.py

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