Alex Mykyta 61bffb7b91 Fix incorrect traversal into externals for read/write buffered regs. #167

2025-11-16 20:29:01 -08:00

..

__init__.py

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

external_ref.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

fixedpoint_counter.rdl

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

fixedpoint_enum.rdl

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

fixedpoint_inconsistent_width.rdl

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

inconsistent_accesswidth.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

multiple_unconditional_assigns.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

sharedextbus.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

signed_counter.rdl

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

signed_enum.rdl

Add signed/fixedpoint properties (#140)

2025-05-15 08:48:44 -07:00

testcase.py

Fix incorrect traversal into externals for read/write buffered regs. #167

2025-11-16 20:29:01 -08:00

unaligned_reg.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

unaligned_stride.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

unbuffered_wide_fields.rdl

Add testcases to cover design validation errors

2025-03-06 22:10:05 -08:00

unsynth_reset1.rdl

Emit error if field that is asynchronously reset uses a dynamic reset value. #129

2025-03-07 19:20:44 -08:00

unsynth_reset2.rdl

Emit error if field that is asynchronously reset uses a dynamic reset value. #129

2025-03-07 19:20:44 -08:00