50 lines
1.7 KiB
Python
50 lines
1.7 KiB
Python
from ..base import CpuifBase
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class AXI4Lite_Cpuif(CpuifBase):
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template_path = "cpuif/axi4lite/axi4lite_tmpl.sv"
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@property
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def port_declaration(self) -> str:
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return "axi4lite_intf.slave s_axil"
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def signal(self, name:str) -> str:
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return "s_axil." + name.upper()
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@property
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def data_width_bytes(self) -> int:
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return self.data_width // 8
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class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
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@property
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def port_declaration(self) -> str:
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lines = [
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"output logic " + self.signal("awready"),
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"input wire " + self.signal("awvalid"),
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f"input wire [{self.addr_width-1}:0] " + self.signal("awaddr"),
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"input wire [2:0] " + self.signal("awprot"),
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"output logic " + self.signal("wready"),
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"input wire " + self.signal("wvalid"),
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f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
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f"input wire [{self.data_width//8-1}:0]" + self.signal("wstrb"),
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"input wire " + self.signal("bready"),
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"output logic " + self.signal("bvalid"),
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"output logic [1:0] " + self.signal("bresp"),
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"output logic " + self.signal("arready"),
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"input wire " + self.signal("arvalid"),
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f"input wire [{self.addr_width-1}:0] " + self.signal("araddr"),
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"input wire [2:0] " + self.signal("arprot"),
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"input wire " + self.signal("rready"),
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"output logic " + self.signal("rvalid"),
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f"output logic [{self.data_width-1}:0] " + self.signal("rdata"),
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"output logic [1:0] " + self.signal("rresp"),
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]
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return ",\n".join(lines)
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def signal(self, name:str) -> str:
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return "s_axil_" + name
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