134 lines
4.1 KiB
ReStructuredText
134 lines
4.1 KiB
ReStructuredText
External Components
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===================
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SystemRDL allows some component instances to be defined as "external" elements
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of an address space definition. In the context of this regblock generator,
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the implementation of an external component is left up to the designer. When
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generating the RTL for a regblock, the implementations of external components
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are omitted and instead a user-interface is presented on the
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``hwif_in``/``hwif_out`` i/o structs.
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External component signals on the hardware interface closely follow the semantics
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of the :ref:`cpuif_protocol`.
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Things you should know
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----------------------
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* By default external ``hwif_out`` signals are driven combinationally. An
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optional output retiming stage can be enabled if needed.
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* Due to the uncertain access latency of external components, the regblock will
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always enforce that only one outstanding transaction to an external component
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at a time. This is enforced even if the CPUIF is capable of pipelined accesses
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such as AXI4-Lite.
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External Registers
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------------------
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External registers can be useful if it is necessary to implement a register that
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cannot easily be expressed using SystemRDL semantics. This could be a unique
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access policy, or FIFO-like push/pop registers.
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External registers are annotated as such by using the ``external`` keyword:
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.. code-block:: systemrdl
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# An internal register
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my_reg int_reg;
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# An external register
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external my_reg ext_reg;
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Request
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^^^^^^^
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hwif_out..req
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When asserted, a read or write transfer will be initiated.
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Qualifies all other request signals.
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If a register is wide (``regwidth`` > ``accesswidth``), then the
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``hwif_out..req`` will consist of multiple bits, representing the access
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strobe for each sub-word of the register.
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hwif_out..req_is_wr
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If ``1``, denotes that the current transfer is a write. Otherwise transfer is
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a read.
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hwif_out..wr_data
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Data to be written for the write transfer. This signal is ignored for read
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transfers.
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The bit-width of this signal always matches the CPUIF's bus width,
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regardless of the regwidth.
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hwif_out..wr_biten
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Active-high bit-level write-enable strobes.
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Only asserted bit positions will change the register value during a write
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transfer.
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Read Response
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^^^^^^^^^^^^^
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hwif_in..rd_ack
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Single-cycle strobe indicating a read transfer has completed.
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Qualifies all other read response signals.
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hwif_in..rd_data
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Read response data.
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Write Response
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^^^^^^^^^^^^^^
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hwif_in..wr_ack
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Single-cycle strobe indicating a write transfer has completed.
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External Blocks
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---------------
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Broader external address regions can be represented by external block-like
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components such as ``addrmap``, ``regfile`` or ``mem`` elements.
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To ensure address decoding for external blocks is simple (only requires simple bit-pruning),
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blocks that are external to an exported regblock shall be aligned to their size.
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Request
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^^^^^^^
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hwif_out..req
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When asserted, a read or write transfer will be initiated.
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Qualifies all other request signals.
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hwif_out..addr
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Byte-address of the transfer.
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Address is always relative to the block's local addressing. i.e: The first
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byte within an external block is represented as ``hwif_out..addr`` == 0,
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regardless of the absolute address of the block.
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hwif_out..req_is_wr
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If ``1``, denotes that the current transfer is a write. Otherwise transfer is
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a read.
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hwif_out..wr_data
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Data to be written for the write transfer. This signal is ignored for read
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transfers.
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The bit-width of this signal always matches the CPUIF's bus width,
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regardless of the contents of the block.
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hwif_out..wr_biten
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Active-high bit-level write-enable strobes.
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Only asserted bit positions will change the register value during a write
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transfer.
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Read Response
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^^^^^^^^^^^^^
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hwif_in..rd_ack
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Single-cycle strobe indicating a read transfer has completed.
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Qualifies all other read response signals.
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hwif_in..rd_data
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Read response data.
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Write Response
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^^^^^^^^^^^^^^
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hwif_in..wr_ack
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Single-cycle strobe indicating a write transfer has completed.
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