Alex Mykyta de09f07450 version
2022-03-20 22:35:29 -07:00
2022-02-28 23:11:23 -08:00
2022-03-16 20:54:00 -07:00
2022-03-20 22:35:29 -07:00
2021-06-01 21:57:12 -07:00
2022-02-28 22:10:09 -08:00

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block

Documentation

See the PeakRDL-regblock Documentation for more details

Description
No description provided
Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%