103 lines
4.3 KiB
Systemverilog
103 lines
4.3 KiB
Systemverilog
enum logic [1:0] {
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CPUIF_IDLE,
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CPUIF_BRESP,
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CPUIF_RRESP
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} cpuif_state;
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logic cpuif_prev_was_rd;
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if({{get_resetsignal(cpuif.reset)}}) begin
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cpuif_state <= CPUIF_IDLE;
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cpuif_prev_was_rd <= '0;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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{{cpuif.signal("arready")}} <= '0;
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{{cpuif.signal("awready")}} <= '0;
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{{cpuif.signal("wready")}} <= '0;
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{{cpuif.signal("bvalid")}} <= '0;
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{{cpuif.signal("bresp")}} <= '0;
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{{cpuif.signal("rvalid")}} <= '0;
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{{cpuif.signal("rdata")}} <= '0;
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{{cpuif.signal("rresp")}} <= '0;
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end else begin
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// Load response transfers as they arrive
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if(cpuif_rd_ack) begin
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{{cpuif.signal("rvalid")}} <= '1;
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{{cpuif.signal("rdata")}} <= cpuif_rd_data;
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if(cpuif_rd_err) {{cpuif.signal("rresp")}} <= 2'b10; // SLVERR
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else {{cpuif.signal("rresp")}} <= 2'b00; // OKAY
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end
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if(cpuif_wr_ack) begin
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{{cpuif.signal("bvalid")}} <= '1;
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if(cpuif_wr_err) {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
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else {{cpuif.signal("bresp")}} <= 2'b00; // OKAY
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end
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// Transaction state machine
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case(cpuif_state)
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CPUIF_IDLE: begin
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// round-robin arbitrate between read/write requests
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// Allow read if previous transfer was not a read, or no write is active
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if({{cpuif.signal("arvalid")}} && (!cpuif_prev_was_rd || !{{cpuif.signal("awvalid")}} || !{{cpuif.signal("wvalid")}})) begin
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cpuif_req <= '1;
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cpuif_req_is_wr <= '0;
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{%- if cpuif.data_width == 8 %}
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cpuif_addr <= {{cpuif.signal("araddr")}}[{{cpuif.addr_width-1}}:0];
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{%- else %}
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cpuif_addr <= { {{-cpuif.signal("araddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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{{cpuif.signal("arready")}} <= '1;
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cpuif_state <= CPUIF_RRESP;
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end else if({{cpuif.signal("awvalid")}} && {{cpuif.signal("wvalid")}}) begin
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{{cpuif.signal("awready")}} <= '1;
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{{cpuif.signal("wready")}} <= '1;
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if({{cpuif.signal("wstrb")}} != {{"%d'b" % cpuif.data_width_bytes}}{{"1" * cpuif.data_width_bytes}}) begin
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// Unaligned writes or use of byte strobes is not supported yet
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{{cpuif.signal("bvalid")}} <= '1;
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{{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
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end else begin
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cpuif_req <= '1;
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cpuif_req_is_wr <= '1;
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{%- if cpuif.data_width == 8 %}
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cpuif_addr <= {{cpuif.signal("awaddr")}}[{{cpuif.addr_width-1}}:0];
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{%- else %}
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cpuif_addr <= { {{-cpuif.signal("awaddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
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{%- endif %}
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cpuif_wr_data <= {{cpuif.signal("wdata")}};
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end
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cpuif_state <= CPUIF_BRESP;
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end
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end
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CPUIF_BRESP: begin
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cpuif_req <= '0;
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{{cpuif.signal("awready")}} <= '0;
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{{cpuif.signal("wready")}} <= '0;
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cpuif_prev_was_rd <= '0;
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if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) begin
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{{cpuif.signal("bvalid")}} <= '0;
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cpuif_state <= CPUIF_IDLE;
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end
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end
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CPUIF_RRESP: begin
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cpuif_req <= '0;
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{{cpuif.signal("arready")}} <= '0;
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cpuif_prev_was_rd <= '1;
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if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
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{{cpuif.signal("rvalid")}} <= '0;
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cpuif_state <= CPUIF_IDLE;
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end
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end
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default: begin
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cpuif_state <= CPUIF_IDLE;
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end
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endcase
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end
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end
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