100 lines
4.5 KiB
Python
100 lines
4.5 KiB
Python
from typing import TYPE_CHECKING, Optional
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from systemrdl.walker import RDLListener, RDLWalker, WalkerAction
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if TYPE_CHECKING:
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from systemrdl.node import Node, RegNode, FieldNode, SignalNode, AddressableNode
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from .exporter import RegblockExporter
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class DesignValidator(RDLListener):
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"""
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Performs additional rule-checks on the design that check for limitations
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imposed by this exporter.
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"""
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def __init__(self, exp:'RegblockExporter') -> None:
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self.exp = exp
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self.msg = exp.top_node.env.msg
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def do_validate(self) -> None:
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RDLWalker().walk(self.exp.top_node, self)
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if self.msg.had_error:
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self.msg.fatal(
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"Unable to export due to previous errors"
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)
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def enter_Component(self, node: 'Node') -> Optional[WalkerAction]:
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if node.external and (node != self.exp.top_node):
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self.msg.error(
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"Exporter does not support external components",
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node.inst.inst_src_ref
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)
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# Do not inspect external components. None of my business
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return WalkerAction.SkipDescendants
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return None
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def enter_Signal(self, node: 'SignalNode') -> None:
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# If encountering a CPUIF reset that is nested within the register model,
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# warn that it will be ignored.
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# Only cpuif resets in the top-level node or above will be honored
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if node.get_property('cpuif_reset') and (node.parent != self.exp.top_node):
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self.msg.warning(
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"Only cpuif_reset signals that are instantiated in the top-level "
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"addrmap or above will be honored. Any cpuif_reset signals nested "
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"within children of the addrmap being exported will be ignored.",
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node.inst.inst_src_ref
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)
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def enter_AddressableComponent(self, node: 'AddressableNode') -> None:
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# All registers must be aligned to the internal data bus width
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alignment = self.exp.cpuif.data_width_bytes
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if (node.raw_address_offset % alignment) != 0:
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self.msg.error(
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"Unaligned registers are not supported. Address offset of "
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f"instance '{node.inst_name}' must be a multiple of {alignment}",
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node.inst.inst_src_ref
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)
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if node.is_array and (node.array_stride % alignment) != 0:
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self.msg.error(
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"Unaligned registers are not supported. Address stride of "
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f"instance array '{node.inst_name}' must be a multiple of {alignment}",
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node.inst.inst_src_ref
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)
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def enter_Reg(self, node: 'RegNode') -> None:
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# accesswidth of wide registers must be consistent within the register block
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accesswidth = node.get_property('accesswidth')
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regwidth = node.get_property('regwidth')
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if accesswidth < regwidth:
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# register is 'wide'
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if accesswidth != self.exp.cpuif.data_width:
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self.msg.error(
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f"Multi-word registers that have an accesswidth ({accesswidth}) "
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"that is inconsistent with this regblock's CPU bus width "
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f"({self.exp.cpuif.data_width}) are not supported.",
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node.inst.inst_src_ref
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)
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def enter_Field(self, node: 'FieldNode') -> None:
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# 10.6.1-f: Any field that is software-writable or clear on read shall
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# not span multiple software accessible sub-words (e.g., a 64-bit
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# register with a 32-bit access width may not have a writable field with
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# bits in both the upper and lower half of the register).
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#
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# Interpreting this further - this rule applies any time a field is
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# software-modifiable by any means, including rclr, rset, ruser
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# TODO: suppress this check for registers that have the appropriate
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# buffer_writes/buffer_reads UDP set
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parent_accesswidth = node.parent.get_property('accesswidth')
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parent_regwidth = node.parent.get_property('regwidth')
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if ((parent_accesswidth < parent_regwidth)
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and (node.lsb // parent_accesswidth) != (node.msb // parent_accesswidth)
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and (node.is_sw_writable or node.get_property('onread') is not None)):
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# Field spans across sub-words
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self.msg.error(
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f"Software-modifiable field '{node.inst_name}' shall not span "
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"multiple software-accessible subwords.",
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node.inst.inst_src_ref
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)
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