Files
PeakRDL-regblock/tests/test_cpuif_err_rsp/regblock.rdl
sbaillou d69af23be5 Error response for unmapped address or forbidden read/write access (#168)
* feat: add ability to enable error output on the cpuif, when decoding errors occur (generate_cpuif_err in API).

* fix: move signal to new place (after automatic vers)

* feat: add info about new api (generate_cpuif_err)

* fix: repair readback with latency

* Adding generate_cpuif_err argument to peakrdl-regblock to generate cpuif error response, when the address is decoded incorrectly

* add sw rd or/and wr attribure error response related and add error respone for external mem

* add sw rd or/and wr error response test

* add sw rd or/and wr error response for external register test and fix generation of rtl logic for external register

* add sw rd or/and wr error response for external mem test

* add sw rd or/and wr error response for apb3 imterfaces driver

* add error response test for APB4, AXI4Lite and Avalon interfaces

* rename --generate_cpuif_err to --generate-cpuif-err

* style: minor typo fixes and test clean-up

* refactor: move expected error check inside write/read functions

* feat: add error response check to OBI testbench interface

* feat: split generate-cpuif-err option into err-if-bad-addr and err-if-bad-rw options

* feat: add err_if_bad_addr/rw to cfg_schema

* feat: extend cpuif_err_rsp test to cover all combinations of bad_addr/bad_rw

* style: lint fixes

* fix: removed redundant if node.external condition to help coverage

* Fix dangling hwif_in signals in testcase

---------

Co-authored-by: Denis Trifonov <d.trifonov@yadro.com>
Co-authored-by: Dominik Tanous <tanous@kandou.com>
Co-authored-by: Sebastien Baillou <baillou@kandou.com>
Co-authored-by: Alex Mykyta <amykyta3@users.noreply.github.com>
2025-10-25 18:22:15 -07:00

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addrmap top {
default regwidth = 32;
default sw=rw;
default hw=na;
reg {
field {
sw=rw; hw=na; // Storage element
} f[31:0] = 40;
} r_rw;
reg {
field {
sw=r; hw=na; // Wire/Bus - constant value
} f[31:0] = 80;
} r_r;
reg {
field {
sw=w; hw=r; // Storage element
} f[31:0] = 100;
} r_w;
external reg {
field {
sw=rw; hw=na; // Storage element
} f[31:0];
} er_rw;
external reg {
field {
sw=r; hw=na; // Wire/Bus - constant value
} f[31:0];
} er_r;
external reg {
field {
sw=w; hw=na; // Storage element
} f[31:0];
} er_w;
external mem {
memwidth = 32;
mementries = 2;
} mem_rw @ 0x20;
external mem {
memwidth = 32;
mementries = 2;
sw=r;
} mem_r @ 0x28;
external mem {
memwidth = 32;
mementries = 2;
sw=w;
} mem_w @ 0x30;
};