129 lines
4.7 KiB
Python
129 lines
4.7 KiB
Python
import re
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from typing import TYPE_CHECKING, List, Union
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from systemrdl.node import Node, AddressableNode, RegNode, FieldNode
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if TYPE_CHECKING:
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from .exporter import RegblockExporter
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class AddressDecode:
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def __init__(self, exporter:'RegblockExporter', top_node:AddressableNode):
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self.exporter = exporter
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self.top_node = top_node
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self._indent_level = 0
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# List of address strides for each dimension
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self._array_stride_stack = []
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def get_strobe_struct(self) -> str:
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lines = []
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self._do_struct(lines, self.top_node, is_top=True)
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return "\n".join(lines)
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def get_implementation(self) -> str:
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lines = []
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self._do_address_decode_node(lines, self.top_node)
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return "\n".join(lines)
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def get_access_strobe(self, node: Union[RegNode, FieldNode]) -> str:
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"""
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Returns the Verilog string that represents the register/field's access strobe.
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"""
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if isinstance(node, FieldNode):
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node = node.parent
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path = node.get_rel_path(self.top_node, empty_array_suffix="[!]")
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# replace unknown indexes with incrementing iterators i0, i1, ...
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class repl:
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def __init__(self):
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self.i = 0
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def __call__(self, match):
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s = f'i{self.i}'
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self.i += 1
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return s
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path = re.sub(r'!', repl(), path)
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return "decoded_reg_strb." + path
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#---------------------------------------------------------------------------
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# Struct generation functions
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#---------------------------------------------------------------------------
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@property
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def _indent(self) -> str:
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return " " * self._indent_level
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def _get_node_array_suffix(self, node:AddressableNode) -> str:
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if node.is_array:
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return "".join([f'[{dim}]' for dim in node.array_dimensions])
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return ""
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def _do_struct(self, lines:List[str], node:AddressableNode, is_top:bool = False) -> None:
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if is_top:
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lines.append(f"{self._indent}typedef struct {{")
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else:
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lines.append(f"{self._indent}struct {{")
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self._indent_level += 1
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for child in node.children():
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if isinstance(child, RegNode):
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lines.append(f"{self._indent}logic {child.inst_name}{self._get_node_array_suffix(child)};")
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elif isinstance(child, AddressableNode):
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self._do_struct(lines, child)
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self._indent_level -= 1
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if is_top:
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lines.append(f"{self._indent}}} decoded_reg_strb_t;")
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else:
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lines.append(f"{self._indent}}} {node.inst_name}{self._get_node_array_suffix(node)};")
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#---------------------------------------------------------------------------
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# Access strobe generation functions
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#---------------------------------------------------------------------------
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def _push_array_dims(self, lines:List[str], node:AddressableNode):
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if not node.is_array:
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return
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# Collect strides for each array dimension
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current_stride = node.array_stride
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strides = []
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for dim in reversed(node.array_dimensions):
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strides.append(current_stride)
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current_stride *= dim
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strides.reverse()
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for dim, stride in zip(node.array_dimensions, strides):
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iterator = "i%d" % len(self._array_stride_stack)
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self._array_stride_stack.append(stride)
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lines.append(f"{self._indent}for(int {iterator}=0; {iterator}<{dim}; {iterator}++) begin")
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self._indent_level += 1
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def _pop_array_dims(self, lines:List[str], node:AddressableNode):
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if not node.is_array:
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return
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for _ in node.array_dimensions:
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self._array_stride_stack.pop()
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self._indent_level -= 1
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lines.append(f"{self._indent}end")
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def _get_address_str(self, node:AddressableNode) -> str:
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a = "'h%x" % (node.raw_absolute_address - self.top_node.raw_absolute_address)
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for i, stride in enumerate(self._array_stride_stack):
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a += f" + i{i}*'h{stride:x}"
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return a
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def _do_address_decode_node(self, lines:List[str], node:AddressableNode) -> None:
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for child in node.children():
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if isinstance(child, RegNode):
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self._push_array_dims(lines, child)
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lines.append(f"{self._indent}{self.get_access_strobe(child)} = cpuif_req & (cpuif_addr == {self._get_address_str(child)});")
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self._pop_array_dims(lines, child)
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elif isinstance(child, AddressableNode):
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self._push_array_dims(lines, child)
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self._do_address_decode_node(lines, child)
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self._pop_array_dims(lines, child)
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