112 lines
2.5 KiB
ReStructuredText
112 lines
2.5 KiB
ReStructuredText
Introduction
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============
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PeakRDL-regblock is a free and open-source control & status register (CSR) compiler.
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This code generator that will translate your SystemRDL register descripton into
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a synthesizable SystemVerilog RTL module that can be easily instantiated into
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your hardware design.
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* Generates fully synthesizable SystemVerilog RTL (IEEE 1800-2012)
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* Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
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* Configurable pipelining options for designs with fast clock rates.
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* Broad support for SystemRDL 2.0 features
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Installing
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----------
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.. important::
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This project has no official releases yet and is still under active development!
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Install from `PyPi`_ using pip
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.. code-block:: bash
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# NOT RELEASED YET
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# python3 -m pip install peakrdl-regblock
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.. _PyPi: https://pypi.org/project/peakrdl-regblock
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Quick Start
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-----------
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Below is a simple example that demonstrates how to generate a SystemVerilog
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implementation from SystemRDL source.
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.. code-block:: python
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:emphasize-lines: 2-3, 23-27
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from systemrdl import RDLCompiler, RDLCompileError
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from peakrdl.regblock import RegblockExporter
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from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif
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input_files = [
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"PATH/TO/my_register_block.rdl"
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]
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# Create an instance of the compiler
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rdlc = RDLCompiler()
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try:
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# Compile your RDL files
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for input_file in input_files:
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rdlc.compile_file(input_file)
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# Elaborate the design
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root = rdlc.elaborate()
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except RDLCompileError:
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# A compilation error occurred. Exit with error code
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sys.exit(1)
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# Export a SystemVerilog implementation
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exporter = RegblockExporter()
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exporter.export(
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root, "path/to/output_dir",
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cpuif_cls=APB3_Cpuif
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)
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Links
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-----
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- `Source repository <https://github.com/SystemRDL/PeakRDL-regblock>`_
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- `Release Notes <https://github.com/SystemRDL/PeakRDL-regblock/releases>`_
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- `Issue tracker <https://github.com/SystemRDL/PeakRDL-regblock/issues>`_
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- `PyPi <https://pypi.org/project/peakrdl-regblock>`_
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- `SystemRDL Specification <http://accellera.org/downloads/standards/systemrdl>`_
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.. toctree::
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:hidden:
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self
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architecture
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hwif
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api
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limitations
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.. toctree::
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:hidden:
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:caption: CPU Interfaces
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cpuif/introduction
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cpuif/apb3
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cpuif/axi4lite
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cpuif/passthrough
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cpuif/internal_protocol
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cpuif/advanced
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.. toctree::
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:hidden:
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:caption: Property Support
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props/field
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props/reg
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props/addrmap
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props/signal
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props/rhs_props
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