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e7e941d27b308a98b60ef6d0b04855e41afb10fc
PeakRDL-regblock/test/lib
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Alex Mykyta 0fa26f2030 Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions
2022-02-15 23:04:28 -08:00
..
cpuifs
Enhance AXI4-Lite CPU Interface to support high performance pipelined transactions
2022-02-15 23:04:28 -08:00
simulators
Rework cpuif to support transaction pipelining. Add more docs. update simulator
2022-02-13 17:25:45 -08:00
__init__.py
testcase framework
2021-12-04 17:31:12 -08:00
regblock_testcase.py
Rework cpuif to support transaction pipelining. Add more docs. update simulator
2022-02-13 17:25:45 -08:00
sv_line_anchor.py
More testcases & documentation
2021-12-04 17:33:35 -08:00
tb_base.sv
Signals working!
2021-12-15 22:03:57 -08:00
test_params.py
Add AXI4-Lite CPUIF
2022-01-31 23:11:31 -08:00
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