182 lines
5.3 KiB
Systemverilog
182 lines
5.3 KiB
Systemverilog
{% extends "lib/tb_base.sv" %}
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{%- block dut_support %}
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{% sv_line_anchor %}
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external_block #(
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.ADDR_WIDTH(3)
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) mem_rw_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mem_rw.req),
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.req_is_wr(hwif_out.mem_rw.req_is_wr),
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.addr(hwif_out.mem_rw.addr),
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.wr_data(hwif_out.mem_rw.wr_data),
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.wr_biten(hwif_out.mem_rw.wr_biten),
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.rd_ack(hwif_in.mem_rw.rd_ack),
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.rd_data(hwif_in.mem_rw.rd_data),
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.wr_ack(hwif_in.mem_rw.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(3)
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) mem_ro_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mem_ro.req),
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.req_is_wr(hwif_out.mem_ro.req_is_wr),
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.addr(hwif_out.mem_ro.addr),
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.wr_data(32'b0),
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.wr_biten(32'b0),
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.rd_ack(hwif_in.mem_ro.rd_ack),
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.rd_data(hwif_in.mem_ro.rd_data),
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.wr_ack(hwif_in.mem_ro.wr_ack)
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);
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external_block #(
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.ADDR_WIDTH(3)
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) mem_wo_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.mem_wo.req),
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.req_is_wr(hwif_out.mem_wo.req_is_wr),
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.addr(hwif_out.mem_wo.addr),
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.wr_data(hwif_out.mem_wo.wr_data),
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.wr_biten(hwif_out.mem_wo.wr_biten),
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.rd_ack(),
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.rd_data(),
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.wr_ack(hwif_in.mem_wo.wr_ack)
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);
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assign hwif_in.mem_wo.rd_ack = '0;
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assign hwif_in.mem_wo.rd_data = '0;
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external_block #(
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.ADDR_WIDTH(4)
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) external_rf_inst (
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.clk(clk),
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.rst(rst),
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.req(hwif_out.external_rf.req),
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.req_is_wr(hwif_out.external_rf.req_is_wr),
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.addr(hwif_out.external_rf.addr),
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.wr_data(hwif_out.external_rf.wr_data),
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.wr_biten(hwif_out.external_rf.wr_biten),
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.rd_ack(hwif_in.external_rf.rd_ack),
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.rd_data(hwif_in.external_rf.rd_data),
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.wr_ack(hwif_in.external_rf.wr_ack)
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);
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{%- endblock %}
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{% block seq %}
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logic wr_err;
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logic expected_wr_err;
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logic expected_rd_err;
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logic bad_addr_expected_err;
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logic bad_rw_expected_wr_err;
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logic bad_rw_expected_rd_err;
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logic [7:0] addr;
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{% sv_line_anchor %}
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##1;
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cb.rst <= '0;
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##1;
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{%- if testcase.err_if_bad_addr %}
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bad_addr_expected_err = 1'b1;
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{%- else %}
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bad_addr_expected_err = 1'b0;
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{%- endif %}
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{%- if testcase.err_if_bad_rw %}
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bad_rw_expected_wr_err = 1'b1;
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bad_rw_expected_rd_err = 1'b1;
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{%- else %}
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bad_rw_expected_wr_err = 1'b0;
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bad_rw_expected_rd_err = 1'b0;
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{%- endif %}
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// r_rw - sw=rw; hw=na; // Storage element
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addr = 'h0;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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cpuif.assert_read(addr, 40, .expects_err(expected_rd_err));
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cpuif.write('h0, 61, .expects_err(expected_wr_err));
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cpuif.assert_read('h0, 61, .expects_err(expected_rd_err));
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// r_r - sw=r; hw=na; // Wire/Bus - constant value
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addr = 'h4;
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expected_rd_err = 'h0;
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expected_wr_err = bad_rw_expected_wr_err;
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cpuif.assert_read(addr, 80, .expects_err(expected_rd_err));
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cpuif.write(addr, 81, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 80, .expects_err(expected_rd_err));
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// r_wo - sw=w; hw=r; // Storage element
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addr = 'h8;
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expected_rd_err = bad_rw_expected_rd_err;
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expected_wr_err = 'h0;
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(cb.hwif_out.r_wo.f.value == 100);
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cpuif.write(addr, 101, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(cb.hwif_out.r_wo.f.value == 101);
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// Reading/writing from/to non existing register
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addr = 'h18;
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cpuif.assert_read(addr, 0, .expects_err(bad_addr_expected_err));
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cpuif.write(addr, 'h8C, .expects_err(bad_addr_expected_err));
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// Reading/writing from/to combined read AND write only register
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addr = 'h1C;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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cpuif.assert_read(addr, 200, .expects_err(expected_rd_err));
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cpuif.write(addr, 'h8C, .expects_err(expected_wr_err));
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// External memories
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// mem_rw - sw=rw;
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addr = 'h20;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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mem_rw_inst.mem[0] = 'h8C;
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cpuif.assert_read(addr, 'h8C, .expects_err(expected_rd_err));
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cpuif.write(addr, 'h8D, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'h8D, .expects_err(expected_rd_err));
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// mem_r - sw=r;
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addr = 'h28;
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expected_rd_err = 'h0;
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expected_wr_err = bad_rw_expected_wr_err;
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mem_ro_inst.mem[0] = 'hB4;
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cpuif.assert_read(addr, 'hB4, .expects_err(expected_rd_err));
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cpuif.write(addr, 'hB5, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'hB4, .expects_err(expected_rd_err));
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// mem_w - sw=w;
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addr = 'h30;
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expected_rd_err = bad_rw_expected_rd_err;
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expected_wr_err = 'h0;
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mem_wo_inst.mem[0] = 'hC8;
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(mem_wo_inst.mem[0] == 'hC8);
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cpuif.write(addr, 'hC9, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 0, .expects_err(expected_rd_err));
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assert(mem_wo_inst.mem[0] == 'hC9);
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// External rf;
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addr = 'h40;
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expected_rd_err = 'h0;
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expected_wr_err = 'h0;
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cpuif.assert_read(addr, 'h0, .expects_err(expected_rd_err));
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cpuif.write(addr, 'hD0, .expects_err(expected_wr_err));
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cpuif.assert_read(addr, 'hD0, .expects_err(expected_rd_err));
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{% endblock %}
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