116 lines
3.7 KiB
Python
116 lines
3.7 KiB
Python
import os
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from typing import Union
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import jinja2 as jj
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from systemrdl.node import AddrmapNode, RootNode
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from .addr_decode import AddressDecode
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from .field_logic import FieldLogic
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from .dereferencer import Dereferencer
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from .readback_mux import ReadbackMux
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from .signals import InferredSignal, SignalBase
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from .cpuif.apb4 import APB4_Cpuif
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from .hwif import Hwif
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from .utils import get_always_ff_event
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class RegblockExporter:
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def __init__(self, **kwargs):
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user_template_dir = kwargs.pop("user_template_dir", None)
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# Check for stray kwargs
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if kwargs:
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raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
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self.top_node = None # type: AddrmapNode
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self.hwif = None # type: Hwif
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self.address_decode = AddressDecode(self)
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self.field_logic = FieldLogic(self)
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self.readback_mux = ReadbackMux(self)
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self.dereferencer = Dereferencer(self)
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self.default_resetsignal = InferredSignal("rst")
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if user_template_dir:
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loader = jj.ChoiceLoader([
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jj.FileSystemLoader(user_template_dir),
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jj.FileSystemLoader(os.path.dirname(__file__)),
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jj.PrefixLoader({
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'user': jj.FileSystemLoader(user_template_dir),
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'base': jj.FileSystemLoader(os.path.dirname(__file__)),
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}, delimiter=":")
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])
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else:
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loader = jj.ChoiceLoader([
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jj.FileSystemLoader(os.path.dirname(__file__)),
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jj.PrefixLoader({
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'base': jj.FileSystemLoader(os.path.dirname(__file__)),
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}, delimiter=":")
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])
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self.jj_env = jj.Environment(
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loader=loader,
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undefined=jj.StrictUndefined,
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)
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def export(self, node: Union[RootNode, AddrmapNode], output_path:str, **kwargs):
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# If it is the root node, skip to top addrmap
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if isinstance(node, RootNode):
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self.top_node = node.top
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else:
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self.top_node = node
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cpuif_cls = kwargs.pop("cpuif_cls", APB4_Cpuif)
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hwif_cls = kwargs.pop("hwif_cls", Hwif)
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module_name = kwargs.pop("module_name", self.top_node.inst_name)
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package_name = kwargs.pop("package_name", module_name + "_pkg")
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# Check for stray kwargs
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if kwargs:
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raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
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# TODO: Scan design...
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# TODO: derive this from somewhere
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cpuif_reset = self.default_resetsignal
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reset_signals = set([cpuif_reset, self.default_resetsignal])
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cpuif = cpuif_cls(
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self,
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cpuif_reset=cpuif_reset, # TODO:
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data_width=32, # TODO: derive from the accesswidth used by regs
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addr_width=32 # TODO:
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)
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self.hwif = hwif_cls(
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self,
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package_name=package_name,
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)
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# Build Jinja template context
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context = {
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"module_name": module_name,
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"data_width": 32, # TODO:
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"addr_width": 32, # TODO:
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"reset_signals": reset_signals,
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"cpuif_reset": cpuif_reset,
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"user_signals": [], # TODO:
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"interrupts": [], # TODO:
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"cpuif": cpuif,
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"hwif": self.hwif,
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"address_decode": self.address_decode,
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"field_logic": self.field_logic,
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"readback_mux": self.readback_mux,
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"get_always_ff_event": get_always_ff_event,
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}
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# Write out design
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template = self.jj_env.get_template("module_tmpl.sv")
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stream = template.stream(context)
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stream.dump(output_path)
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