80 lines
3.1 KiB
Systemverilog
80 lines
3.1 KiB
Systemverilog
{%- if cpuif.is_interface -%}
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`ifndef SYNTHESIS
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initial begin
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assert_bad_addr_width: assert($bits({{cpuif.signal("addr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
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else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("addr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("wdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("wdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
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end
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`endif
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{% endif -%}
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// State & holding regs
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logic is_active; // A request is being served (not yet fully responded)
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logic gnt_q; // one-cycle grant for A-channel
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logic rsp_pending; // response ready but not yet accepted by manager
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logic [{{cpuif.data_width-1}}:0] rsp_rdata_q;
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logic rsp_err_q;
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logic [$bits({{cpuif.signal("rid")}})-1:0] rid_q;
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// Latch AID on accept to echo back the response
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if ({{get_resetsignal(cpuif.reset)}}) begin
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is_active <= 1'b0;
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gnt_q <= 1'b0;
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rsp_pending <= 1'b0;
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rsp_rdata_q <= '0;
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rsp_err_q <= 1'b0;
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rid_q <= '0;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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cpuif_wr_biten <= '0;
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end else begin
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// defaults
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cpuif_req <= 1'b0;
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gnt_q <= {{cpuif.signal("req")}} & ~is_active;
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// Accept new request when idle
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if (~is_active) begin
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if ({{cpuif.signal("req")}}) begin
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is_active <= 1'b1;
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cpuif_req <= 1'b1;
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cpuif_req_is_wr <= {{cpuif.signal("we")}};
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cpuif_addr <= {{cpuif.signal("addr")}};
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cpuif_wr_data <= {{cpuif.signal("wdata")}};
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rid_q <= {{cpuif.signal("aid")}};
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for (int i = 0; i < {{cpuif.data_width_bytes}}; i++) begin
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cpuif_wr_biten[i*8 +: 8] <= {8{ {{cpuif.signal("be")}}[i] }};
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end
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end
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end
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// Capture response
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if (is_active && (cpuif_rd_ack || cpuif_wr_ack)) begin
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rsp_pending <= 1'b1;
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rsp_rdata_q <= cpuif_rd_data;
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rsp_err_q <= cpuif_rd_err | cpuif_wr_err;
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// NOTE: Keep 'is_active' asserted until the external R handshake completes
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end
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// Complete external R-channel handshake only if manager ready
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if (rsp_pending && {{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
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rsp_pending <= 1'b0;
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is_active <= 1'b0; // free to accept the next request
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end
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end
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end
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// R-channel outputs (held stable while rsp_pending=1)
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assign {{cpuif.signal("rvalid")}} = rsp_pending;
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assign {{cpuif.signal("rdata")}} = rsp_rdata_q;
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assign {{cpuif.signal("err")}} = rsp_err_q;
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assign {{cpuif.signal("rid")}} = rid_q;
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// A-channel grant (registered one-cycle pulse when we accept a request)
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assign {{cpuif.signal("gnt")}} = gnt_q;
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