From 3419fd6a61b3a375d501ba6ebbb3dd523ccee8dc Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 23 Nov 2025 22:02:53 -0800 Subject: [PATCH] Update regs --- requirements.txt | 1 + sim/alibaba_pcie.py | 50 ++++---- sim/alibaba_pcie_top_regs.py | 1 + src/regs/alibaba_pcie_top_regs.py | 165 ++++++++++++++++++++++++++ src/regs/alibaba_pcie_top_regs.sv | 4 +- src/regs/alibaba_pcie_top_regs_pkg.sv | 4 +- src/regs/compile_regs.sh | 3 +- 7 files changed, 203 insertions(+), 25 deletions(-) create mode 120000 sim/alibaba_pcie_top_regs.py create mode 100644 src/regs/alibaba_pcie_top_regs.py diff --git a/requirements.txt b/requirements.txt index eda346a..2f76c2c 100644 --- a/requirements.txt +++ b/requirements.txt @@ -7,4 +7,5 @@ rtl-manifest build_fpga fpga-sim peakrdl +peakrdl-python-regmap git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb \ No newline at end of file diff --git a/sim/alibaba_pcie.py b/sim/alibaba_pcie.py index 2fca24f..36bf6fe 100644 --- a/sim/alibaba_pcie.py +++ b/sim/alibaba_pcie.py @@ -10,6 +10,8 @@ from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice from baser import BaseRSerdesSource, BaseRSerdesSink +from alibaba_pcie_top_regs import alibaba_pcie_top_regsClass + CLK_PERIOD = 4 class TB: @@ -146,28 +148,36 @@ async def test_sanity(dut): await mem.write(0, message) + regmap = alibaba_pcie_top_regsClass() + pcie_dma_rd = regmap.pcie_top_regs.pcie_dma_regs.dma_rd + pcie_dma_wr = regmap.pcie_top_regs.pcie_dma_regs.dma_wr + + eth_dma_rd = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_rd + eth_dma_wr = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_wr + + # DMA from host to dma memory - await dev_bar0.write_dword(0x0, 0x00000000) - await dev_bar0.write_dword(0x4, 0x00000000) - await dev_bar0.write_dword(0x8, 0x00000000) - await dev_bar0.write_dword(0xc, len(message)) - await dev_bar0.write_dword(0x10, 0x00000001) + await dev_bar0.write_dword(pcie_dma_rd.src_addr_low.addr, 0x00000000) + await dev_bar0.write_dword(pcie_dma_rd.src_addr_high.addr, 0x00000000) + await dev_bar0.write_dword(pcie_dma_rd.dst_addr.addr, 0x00000000) + await dev_bar0.write_dword(pcie_dma_rd.length.addr, len(message)) + await dev_bar0.write_dword(pcie_dma_rd.trigger.addr, 0x00000001) await Timer(1, "us") # Set up stream to memory DMA to store ethernet frame - await dev_bar0.write_dword(0x180, 0x00000000) - await dev_bar0.write_dword(0x184, 0x00000000) - await dev_bar0.write_dword(0x188, 0x00000000) - await dev_bar0.write_dword(0x18c, len(message)) - await dev_bar0.write_dword(0x190, 0x00000001) + await dev_bar0.write_dword(eth_dma_wr.src_addr.addr, 0x00000000) + await dev_bar0.write_dword(eth_dma_wr.dst_addr_low.addr, 0x00000000) + await dev_bar0.write_dword(eth_dma_wr.dst_addr_high.addr, 0x00000000) + await dev_bar0.write_dword(eth_dma_wr.length.addr, len(message)) + await dev_bar0.write_dword(eth_dma_wr.trigger.addr, 0x00000001) # Trigger memory to stream dma to send ethernet frame - await dev_bar0.write_dword(0x1a0, 0x00000000) - await dev_bar0.write_dword(0x1a4, 0x00000000) - await dev_bar0.write_dword(0x1a8, 0x00000000) - await dev_bar0.write_dword(0x1ac, len(message)) - await dev_bar0.write_dword(0x1b0, 0x00000001) + await dev_bar0.write_dword(eth_dma_rd.src_addr_low.addr, 0x00000000) + await dev_bar0.write_dword(eth_dma_rd.src_addr_high.addr, 0x00000000) + await dev_bar0.write_dword(eth_dma_rd.dst_addr.addr, 0x00000000) + await dev_bar0.write_dword(eth_dma_rd.length.addr, len(message)) + await dev_bar0.write_dword(eth_dma_rd.trigger.addr, 0x00000001) rx_frame = await tb.serdes_sinks[0].recv() @@ -178,11 +188,11 @@ async def test_sanity(dut): await Timer(1, "us") # DMA from dma memory to host - await dev_bar0.write_dword(0x20, 0x00000100) - await dev_bar0.write_dword(0x24, 0x00000000) - await dev_bar0.write_dword(0x28, 0x00000000) - await dev_bar0.write_dword(0x2c, len(message)) - await dev_bar0.write_dword(0x30, 0x00000001) + await dev_bar0.write_dword(pcie_dma_wr.src_addr.addr, 0x00000000) + await dev_bar0.write_dword(pcie_dma_wr.dst_addr_low.addr, 0x00000000) + await dev_bar0.write_dword(pcie_dma_wr.dst_addr_high.addr, 0x00000000) + await dev_bar0.write_dword(pcie_dma_wr.length.addr, len(message)) + await dev_bar0.write_dword(pcie_dma_wr.trigger.addr, 0x00000001) await Timer(1, "us") diff --git a/sim/alibaba_pcie_top_regs.py b/sim/alibaba_pcie_top_regs.py new file mode 120000 index 0000000..7795b14 --- /dev/null +++ b/sim/alibaba_pcie_top_regs.py @@ -0,0 +1 @@ +../src/regs/alibaba_pcie_top_regs.py \ No newline at end of file diff --git a/src/regs/alibaba_pcie_top_regs.py b/src/regs/alibaba_pcie_top_regs.py new file mode 100644 index 0000000..736cb6a --- /dev/null +++ b/src/regs/alibaba_pcie_top_regs.py @@ -0,0 +1,165 @@ +class AddrNode(): + addr: int +class alibaba_pcie_top_regsClass(AddrNode): + class pcie_top_regsClass(AddrNode): + class pcie_dma_regsClass(AddrNode): + class dma_rdClass(AddrNode): + class src_addr_lowClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class src_addr_highClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class dst_addrClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class lengthClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class triggerClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class doneClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + def __init__(self, addr: int = 0): + self.addr = addr + self.src_addr_low = self.src_addr_lowClass(self.addr + 0) + self.src_addr_high = self.src_addr_highClass(self.addr + 4) + self.dst_addr = self.dst_addrClass(self.addr + 8) + self.length = self.lengthClass(self.addr + 12) + self.trigger = self.triggerClass(self.addr + 16) + self.done = self.doneClass(self.addr + 20) + class dma_wrClass(AddrNode): + class dst_addr_lowClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class dst_addr_highClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class src_addrClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class lengthClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class triggerClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class doneClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + def __init__(self, addr: int = 0): + self.addr = addr + self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0) + self.dst_addr_high = self.dst_addr_highClass(self.addr + 4) + self.src_addr = self.src_addrClass(self.addr + 8) + self.length = self.lengthClass(self.addr + 12) + self.trigger = self.triggerClass(self.addr + 16) + self.done = self.doneClass(self.addr + 20) + def __init__(self, addr: int = 0): + self.addr = addr + self.dma_rd = self.dma_rdClass(self.addr + 0) + self.dma_wr = self.dma_wrClass(self.addr + 32) + def __init__(self, addr: int = 0): + self.addr = addr + self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 0) + class eth_dma_wrapper_regsClass(AddrNode): + class eth_mac_25g_us_regsClass(AddrNode): + class commonClass(AddrNode): + class xcvr_gtpowergood_outClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class xcvr_qpll0lock_outClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class xcvr_qpll1lock_outClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + def __init__(self, addr: int = 0): + self.addr = addr + self.xcvr_gtpowergood_out = self.xcvr_gtpowergood_outClass(self.addr + 0) + self.xcvr_qpll0lock_out = self.xcvr_qpll0lock_outClass(self.addr + 4) + self.xcvr_qpll1lock_out = self.xcvr_qpll1lock_outClass(self.addr + 8) + class lanesClass(AddrNode): + class rx_block_lockClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class rx_statusClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + def __init__(self, addr: int = 0): + self.addr = addr + self.rx_block_lock = self.rx_block_lockClass(self.addr + 0) + self.rx_status = self.rx_statusClass(self.addr + 4) + def __init__(self, addr: int = 0): + self.addr = addr + self.common = self.commonClass(self.addr + 0) + self.lanes = [self.lanesClass(self.addr + 32 + 8*i) for i in range(2)] + class pcie_dma_regsClass(AddrNode): + class dma_rdClass(AddrNode): + class src_addr_lowClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class src_addr_highClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class dst_addrClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class lengthClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class triggerClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class doneClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + def __init__(self, addr: int = 0): + self.addr = addr + self.src_addr_low = self.src_addr_lowClass(self.addr + 0) + self.src_addr_high = self.src_addr_highClass(self.addr + 4) + self.dst_addr = self.dst_addrClass(self.addr + 8) + self.length = self.lengthClass(self.addr + 12) + self.trigger = self.triggerClass(self.addr + 16) + self.done = self.doneClass(self.addr + 20) + class dma_wrClass(AddrNode): + class dst_addr_lowClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class dst_addr_highClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class src_addrClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class lengthClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class triggerClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + class doneClass(AddrNode): + def __init__(self, addr: int = 0): + self.addr = addr + def __init__(self, addr: int = 0): + self.addr = addr + self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0) + self.dst_addr_high = self.dst_addr_highClass(self.addr + 4) + self.src_addr = self.src_addrClass(self.addr + 8) + self.length = self.lengthClass(self.addr + 12) + self.trigger = self.triggerClass(self.addr + 16) + self.done = self.doneClass(self.addr + 20) + def __init__(self, addr: int = 0): + self.addr = addr + self.dma_rd = self.dma_rdClass(self.addr + 0) + self.dma_wr = self.dma_wrClass(self.addr + 32) + def __init__(self, addr: int = 0): + self.addr = addr + self.eth_mac_25g_us_regs = self.eth_mac_25g_us_regsClass(self.addr + 0) + self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 128) + def __init__(self, addr: int = 0): + self.addr = addr + self.pcie_top_regs = self.pcie_top_regsClass(self.addr + 0) + self.eth_dma_wrapper_regs = self.eth_dma_wrapper_regsClass(self.addr + 256) diff --git a/src/regs/alibaba_pcie_top_regs.sv b/src/regs/alibaba_pcie_top_regs.sv index 46200e0..742ee0e 100644 --- a/src/regs/alibaba_pcie_top_regs.sv +++ b/src/regs/alibaba_pcie_top_regs.sv @@ -3,8 +3,8 @@ // Description: CPU Interface Bus Decoder // Author: PeakRDL-BusDecoder // License: LGPL-3.0 -// Date: 2025-11-22 -// Version: 0.5.0 +// Date: 2025-11-23 +// Version: 0.6.0 // Links: // - https://github.com/arnavsacheti/PeakRDL-BusDecoder //========================================================== diff --git a/src/regs/alibaba_pcie_top_regs_pkg.sv b/src/regs/alibaba_pcie_top_regs_pkg.sv index 9a9655b..71d2538 100644 --- a/src/regs/alibaba_pcie_top_regs_pkg.sv +++ b/src/regs/alibaba_pcie_top_regs_pkg.sv @@ -3,8 +3,8 @@ // Description: CPU Interface Bus Decoder Package // Author: PeakRDL-BusDecoder // License: LGPL-3.0 -// Date: 2025-11-22 -// Version: 0.5.0 +// Date: 2025-11-23 +// Version: 0.6.0 // Links: // - https://github.com/arnavsacheti/PeakRDL-BusDecoder //========================================================== diff --git a/src/regs/compile_regs.sh b/src/regs/compile_regs.sh index c923d1e..2226137 100755 --- a/src/regs/compile_regs.sh +++ b/src/regs/compile_regs.sh @@ -1,3 +1,4 @@ SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl" -peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb \ No newline at end of file +peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb +peakrdl python-regmap -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.py \ No newline at end of file