Create project

src/alibaba_pcie_top.sv

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 11/05/2025 10:00:52 PM
+// Design Name:
+// Module Name: alibaba_pcie_top
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module alibaba_pcie_top(
+    input  wire [7:0] pci_exp_rxp,
+    input  wire [7:0] pci_exp_rxn,
+    output wire [7:0] pci_exp_txp,
+    output wire [7:0] pci_exp_txn,
+
+    output wire [3:0] Led_o,
+
+    input  wire       pcie_mgt_refclk_p,
+    input  wire       pcie_mgt_refclk_n,
+
+    input  wire       pcie_reset_n
+);
+
+
+
+logic clk_pcie_gt;
+logic clk_pcie;
+logic rst_pcie;
+
+logic clk_250;
+logic rst_250;
+
+logic user_lnk_up;
+logic phy_rdy_out;
+
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
+
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(85), .KEEP_W(8)) s_axis_rq();
+taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
+
+taxi_axil_if m_axil_rd();
+taxi_axil_if m_axil_wr();
+
+IBUFDS_GTE4 m_ibufds (
+    .CEB('0),
+    .I(pcie_mgt_refclk_p),
+    .IB(pcie_mgt_refclk_n),
+    .O(clk_pcie_gt),
+    .ODIV2(clk_pcie)
+);
+
+assign Led_o[0] = user_lnk_up;
+assign Led_o[1] = phy_rdy_out; 
+
+taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
+    .clk                (clk_250),
+    .rst                (rst_250),
+
+    .s_axis_cq          (m_axis_cq),
+    .m_axis_cc          (s_axis_cc),
+
+    .m_axil_wr          (m_axil_wr),
+    .m_axil_rd          (m_axil_rd),
+
+    .completer_id       ('0),
+    .completer_id_en    ('0),
+
+    .stat_err_cor       (),
+    .stat_err_uncor     ()
+);
+
+taxi_axil_ram #(
+    .ADDR_W(16)
+) u_taxi_axil_ram (
+    .clk        (clk_250),
+    .rst        (rst_250),
+
+    .s_axil_wr  (m_axil_wr),
+    .s_axil_rd  (m_axil_rd)
+);
+
+taxi_axis_null_snk u_taxi_axis_null_snk (
+    .s_axis     (m_axis_rc)
+);
+
+taxi_axis_null_src u_taxi_axis_null_src (
+    .m_axis     (s_axis_rq)
+);
+
+pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
+    .pci_exp_txn(pci_exp_txn),
+    .pci_exp_txp(pci_exp_txp),
+    .pci_exp_rxn(pci_exp_rxn),
+    .pci_exp_rxp(pci_exp_rxp),
+
+    .user_clk(clk_250),
+    .user_reset(rst_250),
+    .user_lnk_up(user_lnk_up),
+
+    .s_axis_rq_tdata(s_axis_rq.tdata),
+    .s_axis_rq_tkeep(s_axis_rq.tkeep),
+    .s_axis_rq_tlast(s_axis_rq.tlast),
+    .s_axis_rq_tready(s_axis_rq.tready),
+    .s_axis_rq_tuser(s_axis_rq.tuser),
+    .s_axis_rq_tvalid(s_axis_rq.tvalid),
+
+    .m_axis_rc_tdata(m_axis_rc.tdata),
+    .m_axis_rc_tkeep(m_axis_rc.tkeep),
+    .m_axis_rc_tlast(m_axis_rc.tlast),
+    .m_axis_rc_tready(m_axis_rc.tready),
+    .m_axis_rc_tuser(m_axis_rc.tuser),
+    .m_axis_rc_tvalid(m_axis_rc.tvalid),
+
+    .m_axis_cq_tdata(m_axis_cq.tdata),
+    .m_axis_cq_tkeep(m_axis_cq.tkeep),
+    .m_axis_cq_tlast(m_axis_cq.tlast),
+    .m_axis_cq_tready(m_axis_cq.tready),
+    .m_axis_cq_tuser(m_axis_cq.tuser),
+    .m_axis_cq_tvalid(m_axis_cq.tvalid),
+
+    .s_axis_cc_tdata(s_axis_cc.tdata),
+    .s_axis_cc_tkeep(s_axis_cc.tkeep),
+    .s_axis_cc_tlast(s_axis_cc.tlast),
+    .s_axis_cc_tready(s_axis_cc.tready),
+    .s_axis_cc_tuser(s_axis_cc.tuser),
+    .s_axis_cc_tvalid(s_axis_cc.tvalid),
+
+    .cfg_interrupt_int('0),
+    .cfg_interrupt_pending(),
+    .cfg_interrupt_sent('0),
+    .cfg_interrupt_msi_enable(),
+    .cfg_interrupt_msi_mmenable(),
+    .cfg_interrupt_msi_mask_update(),
+    .cfg_interrupt_msi_data(),
+    .cfg_interrupt_msi_select('0),
+    .cfg_interrupt_msi_int('0),
+    .cfg_interrupt_msi_pending_status('0),
+    .cfg_interrupt_msi_pending_status_data_enable('0),
+    .cfg_interrupt_msi_pending_status_function_num('0),
+    .cfg_interrupt_msi_sent(),
+    .cfg_interrupt_msi_fail(),
+    .cfg_interrupt_msi_attr('0),
+    .cfg_interrupt_msi_tph_present('0),
+    .cfg_interrupt_msi_tph_type('0),
+    .cfg_interrupt_msi_tph_st_tag('0),
+    .cfg_interrupt_msi_function_number('0),
+
+    .sys_clk(clk_pcie),
+    .sys_clk_gt(clk_pcie_gt),
+    .sys_reset(pcie_reset_n),
+    .phy_rdy_out(phy_rdy_out)
+);
+
+endmodule