Add eth dma wrapper
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@@ -20,17 +20,25 @@
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//////////////////////////////////////////////////////////////////////////////////
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module alibaba_pcie(
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input wire [7:0] pci_exp_rxp,
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input wire [7:0] pci_exp_rxn,
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output wire [7:0] pci_exp_txp,
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output wire [7:0] pci_exp_txn,
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input wire [7:0] pci_exp_rxp,
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input wire [7:0] pci_exp_rxn,
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output wire [7:0] pci_exp_txp,
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output wire [7:0] pci_exp_txn,
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output wire [3:0] Led_o,
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input wire pcie_mgt_refclk_p,
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input wire pcie_mgt_refclk_n,
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input wire pcie_mgt_refclk_p,
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input wire pcie_mgt_refclk_n,
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input wire pcie_reset_n,
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input wire pcie_reset_n
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input wire sfp_mgt_clk_p,
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input wire sfp_mgt_clk_n,
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output wire [1:0] sfp_txp,
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output wire [1:0] sfp_txn,
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input wire [1:0] sfp_rxp,
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input wire [1:0] sfp_rxn,
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output wire [3:0] Led_o
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);
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@@ -54,7 +62,9 @@ taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
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taxi_axil_if m_axil_rd();
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taxi_axil_if m_axil_wr();
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taxi_apb_if #(.ADDR_W(6)) m_apb();
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taxi_apb_if #(.ADDR_W(7)) s_apb();
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taxi_apb_if #(.ADDR_W(6)) m_apb[2]();
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`ifndef SIM
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IBUFDS_GTE4 m_ibufds (
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@@ -69,6 +79,50 @@ IBUFDS_GTE4 m_ibufds (
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assign Led_o[0] = user_lnk_up;
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assign Led_o[1] = phy_rdy_out;
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
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taxi_apb_interconnect #(
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.M_CNT(2),
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.ADDR_W(7),
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.M_REGIONS(1),
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.M_BASE_ADDR('0),
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.M_ADDR_W({32'd6, 32'd6}),
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.M_SECURE({2{1'b0}})
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) u_apb_interconnect (
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.clk (clk_250),
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.rst (rst_250),
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.s_apb (s_apb),
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.m_apb (m_apb)
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);
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taxi_dma_psdpram #(
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.SIZE(16384)
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) u_taxi_dma_tx_psdpram (
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.clk (clk_250),
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.rst (rst_250),
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.dma_ram_wr (dma_ram_pcie_wr_if),
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.dma_ram_rd (dma_ram_eth_rd_if)
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);
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taxi_dma_psdpram #(
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.SIZE(16384)
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) u_taxi_dma_rx_psdpram(
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.clk (clk_250),
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.rst (rst_250),
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.dma_ram_wr (dma_ram_eth_wr_if),
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.dma_ram_rd (dma_ram_pcie_rd_if)
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);
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taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
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.clk (clk_250),
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.rst (rst_250),
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@@ -93,7 +147,7 @@ taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
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.s_axil_wr (m_axil_wr),
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.s_axil_rd (m_axil_rd),
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.m_apb (m_apb)
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.m_apb (s_apb)
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);
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pcie_dma_wrapper u_pcie_dma_wrapper (
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@@ -103,7 +157,28 @@ pcie_dma_wrapper u_pcie_dma_wrapper (
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.m_axis_rq (s_axis_rq),
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.s_axis_rc (m_axis_rc),
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.s_apb (m_apb)
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.wr_dma_mst (dma_ram_pcie_wr_if),
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.rd_dma_mst (dma_ram_pcie_rd_if),
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.s_apb (m_apb[0])
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);
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eth_dma_wrapper u_eth_dma_wrapper (
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.clk_250 (clk_250),
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.rst_250 (rst_250),
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.sfp_mgt_clk_p (sfp_mgt_clk_p),
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.sfp_mgt_clk_n (sfp_mgt_clk_n),
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.sfp_txp (sfp_txp),
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.sfp_txn (sfp_txn),
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.sfp_rxp (sfp_rxp),
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.sfp_rxn (sfp_rxn),
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.wr_dma_mst (dma_ram_eth_wr_if),
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.rd_dma_mst (dma_ram_eth_rd_if),
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.s_apb (m_apb[1])
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);
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`ifndef SIM
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