From 85cb3cc2a648f8fb4fefa4cb8c9c3109824fc48d Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sat, 22 Nov 2025 16:07:56 -0800 Subject: [PATCH] Use taxi apb interface, finish reorg --- requirements.txt | 2 +- sources.list | 20 ++--- src/alibaba_pcie_top.sv | 28 +++---- src/eth/eth_dma_wrapper.sv | 44 ++++++----- src/eth/regs/compile_regs.sh | 2 +- src/eth/regs/eth_dma_wrapper_regs.sv | 114 +++++++++++---------------- src/eth/sources.list | 6 ++ src/{eth => pcie}/pcie_top.sv | 14 +++- src/pcie/regs/compile_regs.sh | 2 +- src/pcie/regs/pcie_top_regs.sv | 81 +++++++++---------- src/pcie/sources.list | 9 +++ src/regs/alibaba_pcie_top_regs.sv | 114 +++++++++++---------------- src/regs/compile_regs.sh | 3 +- 13 files changed, 209 insertions(+), 230 deletions(-) create mode 100644 src/eth/sources.list rename src/{eth => pcie}/pcie_top.sv (93%) create mode 100644 src/pcie/sources.list diff --git a/requirements.txt b/requirements.txt index 78d5a7c..3243fd1 100644 --- a/requirements.txt +++ b/requirements.txt @@ -7,4 +7,4 @@ rtl-manifest build_fpga fpga-sim peakrdl -git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@dev/downsize_apb_paddr \ No newline at end of file +git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@dev/taxi_apb \ No newline at end of file diff --git a/sources.list b/sources.list index 3ecb754..f57bacf 100644 --- a/sources.list +++ b/sources.list @@ -3,13 +3,15 @@ ip/taxi_eth_phy_25g_us_gty_ch/taxi_eth_phy_25g_us_gty_ch.xci ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci ip/taxi_eth_phy_25g_us_gty_ll_ch/taxi_eth_phy_25g_us_gty_ll_ch.xci ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci -src/alibaba_cloud.xdc -src/alibaba_pcie_top.sv -src/regs/verilator.vlt -src/regs/pcie_dma_regs_pkg.sv -src/regs/pcie_dma_regs.sv -src/pcie_dma_wrapper.sv -src/eth/regs/eth_mac_25g_us_regs_pkg.sv -src/eth/regs/eth_mac_25g_us_regs.sv -src/eth/eth_dma_wrapper.sv + sub/taxi_sources.list + +eth/sources.list +pcie/sources.list + +src/regs/verilator.vlt +src/regs/alibaba_pcie_top_regs_pkg.sv +src/regs/alibaba_pcie_top_regs.sv +src/alibaba_pcie_top.sv + +src/alibaba_cloud.xdc diff --git a/src/alibaba_pcie_top.sv b/src/alibaba_pcie_top.sv index 1875ee4..368771b 100644 --- a/src/alibaba_pcie_top.sv +++ b/src/alibaba_pcie_top.sv @@ -46,30 +46,20 @@ module alibaba_pcie( taxi_axil_if m_axil_rd(); taxi_axil_if m_axil_wr(); -taxi_apb_if #(.ADDR_W(9)) s_apb(); +taxi_apb_if #(.ADDR_W(alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)) s_apb(); -taxi_apb_if #(.ADDR_W(9)) m_apb[2](); +taxi_apb_if #(.ADDR_W(pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)) pcie_apb(); +taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_apb(); taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if(); taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if(); -taxi_apb_interconnect #( - .M_CNT(2), - .ADDR_W(7), - .M_REGIONS(1), - .M_BASE_ADDR('0), - .M_ADDR_W({32'd6, 32'd6}), - .M_SECURE({2{1'b0}}) -) u_apb_interconnect ( - .clk (clk_250), - .rst (rst_250), - +alibaba_pcie_top_regs u_alibaba_pcie_top_regs ( .s_apb (s_apb), - - .m_apb (m_apb) + .m_apb_pcie_top_regs (pcie_apb), + .m_apb_eth_dma_wrapper_regs (eth_apb) ); - taxi_axil_apb_adapter u_taxi_axil_apb_adapter ( .clk (clk_250), .rst (rst_250), @@ -96,7 +86,7 @@ eth_dma_wrapper u_eth_dma_wrapper ( .wr_dma_mst (dma_ram_eth_wr_if), .rd_dma_mst (dma_ram_eth_rd_if), - .s_apb (m_apb[1]) + .s_apb (eth_apb) ); pcie_top u_pcie_top( @@ -117,7 +107,9 @@ pcie_top u_pcie_top( .dma_ram_eth_rd_if (dma_ram_eth_rd_if), .m_axil_rd (m_axil_rd), - .m_axil_wr (m_axil_wr) + .m_axil_wr (m_axil_wr), + + .s_apb (pcie_apb) ); endmodule diff --git a/src/eth/eth_dma_wrapper.sv b/src/eth/eth_dma_wrapper.sv index 52d0979..ed57d4a 100644 --- a/src/eth/eth_dma_wrapper.sv +++ b/src/eth/eth_dma_wrapper.sv @@ -84,22 +84,26 @@ endgenerate taxi_axis_if axis_sfp_stat(); +taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_dma_apb(); +taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb(); + + eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in; eth_mac_25g_us_regs u_eth_mac_25g_us_regs ( .clk (clk_250), .rst (rst_250), - .s_apb_psel (s_apb_eth.psel), - .s_apb_penable (s_apb_eth.penable), - .s_apb_pwrite (s_apb_eth.pwrite), - .s_apb_pprot (s_apb_eth.pprot), - .s_apb_paddr (s_apb_eth.paddr), - .s_apb_pwdata (s_apb_eth.pwdata), - .s_apb_pstrb (s_apb_eth.pstrb), - .s_apb_pready (s_apb_eth.pready), - .s_apb_prdata (s_apb_eth.prdata), - .s_apb_pslverr (s_apb_eth.pslverr), + .s_apb_psel (eth_mac_apb.psel), + .s_apb_penable (eth_mac_apb.penable), + .s_apb_pwrite (eth_mac_apb.pwrite), + .s_apb_pprot (eth_mac_apb.pprot), + .s_apb_paddr (eth_mac_apb.paddr), + .s_apb_pwdata (eth_mac_apb.pwdata), + .s_apb_pstrb (eth_mac_apb.pstrb), + .s_apb_pready (eth_mac_apb.pready), + .s_apb_prdata (eth_mac_apb.prdata), + .s_apb_pslverr (eth_mac_apb.pslverr), .hwif_in (hwif_in), .hwif_out (hwif_out) @@ -300,16 +304,16 @@ pcie_dma_regs u_pcie_dma_regs( .clk (clk_250), .rst (rst_250), - .s_apb_psel (s_apb_dma.psel), - .s_apb_penable (s_apb_dma.penable), - .s_apb_pwrite (s_apb_dma.pwrite), - .s_apb_pprot (s_apb_dma.pprot), - .s_apb_paddr (s_apb_dma.paddr), - .s_apb_pwdata (s_apb_dma.pwdata), - .s_apb_pstrb (s_apb_dma.pstrb), - .s_apb_pready (s_apb_dma.pready), - .s_apb_prdata (s_apb_dma.prdata), - .s_apb_pslverr (s_apb_dma.pslverr), + .s_apb_psel (eth_dma_apb.psel), + .s_apb_penable (eth_dma_apb.penable), + .s_apb_pwrite (eth_dma_apb.pwrite), + .s_apb_pprot (eth_dma_apb.pprot), + .s_apb_paddr (eth_dma_apb.paddr), + .s_apb_pwdata (eth_dma_apb.pwdata), + .s_apb_pstrb (eth_dma_apb.pstrb), + .s_apb_pready (eth_dma_apb.pready), + .s_apb_prdata (eth_dma_apb.prdata), + .s_apb_pslverr (eth_dma_apb.pslverr), .hwif_in (dma_hwif_in), .hwif_out (dma_hwif_out) diff --git a/src/eth/regs/compile_regs.sh b/src/eth/regs/compile_regs.sh index 61729bb..3a58ea9 100755 --- a/src/eth/regs/compile_regs.sh +++ b/src/eth/regs/compile_regs.sh @@ -1,2 +1,2 @@ peakrdl regblock -t eth_mac_25g_us_regs eth_mac_25g_us_regs.rdl -o . --cpuif apb4-flat -peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl -o . --cpuif apb4-flat \ No newline at end of file +peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl -o . --cpuif taxi-apb \ No newline at end of file diff --git a/src/eth/regs/eth_dma_wrapper_regs.sv b/src/eth/regs/eth_dma_wrapper_regs.sv index 6cad28a..923aca6 100644 --- a/src/eth/regs/eth_dma_wrapper_regs.sv +++ b/src/eth/regs/eth_dma_wrapper_regs.sv @@ -11,42 +11,9 @@ module eth_dma_wrapper_regs ( - input logic s_apb_PCLK, - input logic s_apb_PRESETn, - input logic s_apb_PSEL, - input logic s_apb_PENABLE, - input logic s_apb_PWRITE, - input logic [7:0] s_apb_PADDR, - input logic [2:0] s_apb_PPROT, - input logic [31:0] s_apb_PWDATA, - input logic [3:0] s_apb_PSTRB, - output logic [31:0] s_apb_PRDATA, - output logic s_apb_PREADY, - output logic s_apb_PSLVERR, - output logic m_apb_eth_mac_25g_us_regs_PCLK, - output logic m_apb_eth_mac_25g_us_regs_PRESETn, - output logic m_apb_eth_mac_25g_us_regs_PSEL, - output logic m_apb_eth_mac_25g_us_regs_PENABLE, - output logic m_apb_eth_mac_25g_us_regs_PWRITE, - output logic [6:0] m_apb_eth_mac_25g_us_regs_PADDR, - output logic [2:0] m_apb_eth_mac_25g_us_regs_PPROT, - output logic [31:0] m_apb_eth_mac_25g_us_regs_PWDATA, - output logic [3:0] m_apb_eth_mac_25g_us_regs_PSTRB, - input logic [31:0] m_apb_eth_mac_25g_us_regs_PRDATA, - input logic m_apb_eth_mac_25g_us_regs_PREADY, - input logic m_apb_eth_mac_25g_us_regs_PSLVERR, - output logic m_apb_pcie_dma_regs_PCLK, - output logic m_apb_pcie_dma_regs_PRESETn, - output logic m_apb_pcie_dma_regs_PSEL, - output logic m_apb_pcie_dma_regs_PENABLE, - output logic m_apb_pcie_dma_regs_PWRITE, - output logic [5:0] m_apb_pcie_dma_regs_PADDR, - output logic [2:0] m_apb_pcie_dma_regs_PPROT, - output logic [31:0] m_apb_pcie_dma_regs_PWDATA, - output logic [3:0] m_apb_pcie_dma_regs_PSTRB, - input logic [31:0] m_apb_pcie_dma_regs_PRDATA, - input logic m_apb_pcie_dma_regs_PREADY, - input logic m_apb_pcie_dma_regs_PSLVERR + taxi_apb_if.slv s_apb, + taxi_apb_if.mst m_apb_eth_mac_25g_us_regs, + taxi_apb_if.mst m_apb_pcie_dma_regs ); //-------------------------------------------------------------------------- // CPU Bus interface logic @@ -81,38 +48,53 @@ module eth_dma_wrapper_regs ( // Slave <-> Internal CPUIF <-> Master //-------------------------------------------------------------------------- + `ifndef SYNTHESIS + initial begin + assert_bad_addr_width: assert($bits(s_apb.paddr) >= eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH) + else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH); + assert_bad_data_width: assert($bits(s_apb.pwdata) == eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH) + else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH); + end + assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr)) + else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded"); + `endif - assign cpuif_req = s_apb_PSEL; - assign cpuif_wr_en = s_apb_PWRITE; - assign cpuif_rd_en = !s_apb_PWRITE; + assign cpuif_req = s_apb.psel; + assign cpuif_wr_en = s_apb.pwrite; + assign cpuif_rd_en = !s_apb.pwrite; - assign cpuif_wr_addr = s_apb_PADDR; - assign cpuif_rd_addr = s_apb_PADDR; + assign cpuif_wr_addr = s_apb.paddr; + assign cpuif_rd_addr = s_apb.paddr; - assign cpuif_wr_data = s_apb_PWDATA; - assign cpuif_wr_byte_en = s_apb_PSTRB; + assign cpuif_wr_data = s_apb.pwdata; + assign cpuif_wr_byte_en = s_apb.PSTRB; - assign s_apb_PRDATA = cpuif_rd_data; - assign s_apb_PREADY = cpuif_rd_ack; - assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; + assign s_apb.prdata = cpuif_rd_data; + assign s_apb.pready = cpuif_rd_ack; + assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; //-------------------------------------------------------------------------- // Fanout CPU Bus interface signals //-------------------------------------------------------------------------- - assign m_apb_eth_mac_25g_us_regs_PSEL = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs; - assign m_apb_eth_mac_25g_us_regs_PENABLE = s_apb_PENABLE; - assign m_apb_eth_mac_25g_us_regs_PWRITE = cpuif_wr_sel.eth_mac_25g_us_regs; - assign m_apb_eth_mac_25g_us_regs_PADDR = s_apb_PADDR[6:0]; - assign m_apb_eth_mac_25g_us_regs_PPROT = s_apb_PPROT; - assign m_apb_eth_mac_25g_us_regs_PWDATA = cpuif_wr_data; - assign m_apb_eth_mac_25g_us_regs_PSTRB = cpuif_wr_byte_en; - assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs; - assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE; - assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs; - assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0]; - assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT; - assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data; - assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en; + assign m_apb_eth_mac_25g_us_regs.psel = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs; + assign m_apb_eth_mac_25g_us_regs.penable = s_apb.penable; + assign m_apb_eth_mac_25g_us_regs.pwrite = cpuif_wr_sel.eth_mac_25g_us_regs; + assign m_apb_eth_mac_25g_us_regs.paddr = s_apb.paddr; + assign m_apb_eth_mac_25g_us_regs.pprot = s_apb.pprot; + assign m_apb_eth_mac_25g_us_regs.pwdata = cpuif_wr_data; + assign m_apb_eth_mac_25g_us_regs.pstrb = cpuif_wr_byte_en; + assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs; + assign m_apb_pcie_dma_regs.penable = s_apb.penable; + assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs; + assign m_apb_pcie_dma_regs.paddr = s_apb.paddr; + assign m_apb_pcie_dma_regs.pprot = s_apb.pprot; + assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data; + assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en; + + //-------------------------------------------------------------------------- + // Intermediate signals for interface array fanin + //-------------------------------------------------------------------------- + //-------------------------------------------------------------------------- // Fanin CPU Bus interface signals @@ -122,18 +104,18 @@ module eth_dma_wrapper_regs ( cpuif_rd_err = '0; cpuif_rd_data = '0; if (cpuif_rd_sel.eth_mac_25g_us_regs || cpuif_wr_sel.eth_mac_25g_us_regs) begin - cpuif_rd_ack = m_apb_eth_mac_25g_us_regs_PREADY; - cpuif_rd_err = m_apb_eth_mac_25g_us_regs_PSLVERR; + cpuif_rd_ack = m_apb_eth_mac_25g_us_regs.pready; + cpuif_rd_err = m_apb_eth_mac_25g_us_regs.pslverr; end if (cpuif_rd_sel.eth_mac_25g_us_regs) begin - cpuif_rd_data = m_apb_eth_mac_25g_us_regs_PRDATA; + cpuif_rd_data = m_apb_eth_mac_25g_us_regs.prdata; end if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin - cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY; - cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR; + cpuif_rd_ack = m_apb_pcie_dma_regs.pready; + cpuif_rd_err = m_apb_pcie_dma_regs.pslverr; end if (cpuif_rd_sel.pcie_dma_regs) begin - cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA; + cpuif_rd_data = m_apb_pcie_dma_regs.prdata; end end diff --git a/src/eth/sources.list b/src/eth/sources.list new file mode 100644 index 0000000..9cdb3c0 --- /dev/null +++ b/src/eth/sources.list @@ -0,0 +1,6 @@ +src/eth/regs/eth_dma_wrapper_regs_pkg.sv +src/eth/regs/eth_dma_wrapper_regs.sv +src/eth/regs/eth_mac_25g_us_regs_pkg.sv +src/eth/regs/eth_mac_25g_us_regs.sv + +eth_dma_wrapper.sv \ No newline at end of file diff --git a/src/eth/pcie_top.sv b/src/pcie/pcie_top.sv similarity index 93% rename from src/eth/pcie_top.sv rename to src/pcie/pcie_top.sv index 8c7f56f..1793fc4 100644 --- a/src/eth/pcie_top.sv +++ b/src/pcie/pcie_top.sv @@ -16,7 +16,9 @@ module pcie_top( taxi_dma_ram_if.rd_slv dma_ram_eth_rd_if, taxi_axil_if.rd_mst m_axil_rd, - taxi_axil_if.wr_mst m_axil_wr + taxi_axil_if.wr_mst m_axil_wr, + + taxi_apb_if.slv s_apb ); @@ -39,6 +41,9 @@ taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc(); taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if(); taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if(); +taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) pcie_dma_apb(); + + `ifndef SIM IBUFDS_GTE4 m_ibufds ( .CEB('0), @@ -49,6 +54,11 @@ IBUFDS_GTE4 m_ibufds ( ); `endif +pcie_top_regs u_pcie_top_regs ( + .s_apb (s_apb), + .m_apb_pcie_dma_regs(pcie_dma_apb) +) + taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master ( .clk (clk_250), .rst (rst_250), @@ -96,7 +106,7 @@ pcie_dma_wrapper u_pcie_dma_wrapper ( .wr_dma_mst (dma_ram_pcie_wr_if), .rd_dma_mst (dma_ram_pcie_rd_if), - .s_apb (m_apb[0]) + .s_apb (pcie_dma_apb) ); `ifndef SIM diff --git a/src/pcie/regs/compile_regs.sh b/src/pcie/regs/compile_regs.sh index 45e6891..0b243ac 100755 --- a/src/pcie/regs/compile_regs.sh +++ b/src/pcie/regs/compile_regs.sh @@ -1,2 +1,2 @@ peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat -peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif apb4-flat \ No newline at end of file +peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif taxi-apb \ No newline at end of file diff --git a/src/pcie/regs/pcie_top_regs.sv b/src/pcie/regs/pcie_top_regs.sv index 2824162..e22402b 100644 --- a/src/pcie/regs/pcie_top_regs.sv +++ b/src/pcie/regs/pcie_top_regs.sv @@ -11,30 +11,8 @@ module pcie_top_regs ( - input logic s_apb_PCLK, - input logic s_apb_PRESETn, - input logic s_apb_PSEL, - input logic s_apb_PENABLE, - input logic s_apb_PWRITE, - input logic [5:0] s_apb_PADDR, - input logic [2:0] s_apb_PPROT, - input logic [31:0] s_apb_PWDATA, - input logic [3:0] s_apb_PSTRB, - output logic [31:0] s_apb_PRDATA, - output logic s_apb_PREADY, - output logic s_apb_PSLVERR, - output logic m_apb_pcie_dma_regs_PCLK, - output logic m_apb_pcie_dma_regs_PRESETn, - output logic m_apb_pcie_dma_regs_PSEL, - output logic m_apb_pcie_dma_regs_PENABLE, - output logic m_apb_pcie_dma_regs_PWRITE, - output logic [5:0] m_apb_pcie_dma_regs_PADDR, - output logic [2:0] m_apb_pcie_dma_regs_PPROT, - output logic [31:0] m_apb_pcie_dma_regs_PWDATA, - output logic [3:0] m_apb_pcie_dma_regs_PSTRB, - input logic [31:0] m_apb_pcie_dma_regs_PRDATA, - input logic m_apb_pcie_dma_regs_PREADY, - input logic m_apb_pcie_dma_regs_PSLVERR + taxi_apb_if.slv s_apb, + taxi_apb_if.mst m_apb_pcie_dma_regs ); //-------------------------------------------------------------------------- // CPU Bus interface logic @@ -68,31 +46,46 @@ module pcie_top_regs ( // Slave <-> Internal CPUIF <-> Master //-------------------------------------------------------------------------- + `ifndef SYNTHESIS + initial begin + assert_bad_addr_width: assert($bits(s_apb.paddr) >= pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH) + else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH); + assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH) + else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH); + end + assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr)) + else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded"); + `endif - assign cpuif_req = s_apb_PSEL; - assign cpuif_wr_en = s_apb_PWRITE; - assign cpuif_rd_en = !s_apb_PWRITE; + assign cpuif_req = s_apb.psel; + assign cpuif_wr_en = s_apb.pwrite; + assign cpuif_rd_en = !s_apb.pwrite; - assign cpuif_wr_addr = s_apb_PADDR; - assign cpuif_rd_addr = s_apb_PADDR; + assign cpuif_wr_addr = s_apb.paddr; + assign cpuif_rd_addr = s_apb.paddr; - assign cpuif_wr_data = s_apb_PWDATA; - assign cpuif_wr_byte_en = s_apb_PSTRB; + assign cpuif_wr_data = s_apb.pwdata; + assign cpuif_wr_byte_en = s_apb.PSTRB; - assign s_apb_PRDATA = cpuif_rd_data; - assign s_apb_PREADY = cpuif_rd_ack; - assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; + assign s_apb.prdata = cpuif_rd_data; + assign s_apb.pready = cpuif_rd_ack; + assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; //-------------------------------------------------------------------------- // Fanout CPU Bus interface signals //-------------------------------------------------------------------------- - assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs; - assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE; - assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs; - assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0]; - assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT; - assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data; - assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en; + assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs; + assign m_apb_pcie_dma_regs.penable = s_apb.penable; + assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs; + assign m_apb_pcie_dma_regs.paddr = s_apb.paddr; + assign m_apb_pcie_dma_regs.pprot = s_apb.pprot; + assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data; + assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en; + + //-------------------------------------------------------------------------- + // Intermediate signals for interface array fanin + //-------------------------------------------------------------------------- + //-------------------------------------------------------------------------- // Fanin CPU Bus interface signals @@ -102,11 +95,11 @@ module pcie_top_regs ( cpuif_rd_err = '0; cpuif_rd_data = '0; if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin - cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY; - cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR; + cpuif_rd_ack = m_apb_pcie_dma_regs.pready; + cpuif_rd_err = m_apb_pcie_dma_regs.pslverr; end if (cpuif_rd_sel.pcie_dma_regs) begin - cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA; + cpuif_rd_data = m_apb_pcie_dma_regs.prdata; end end diff --git a/src/pcie/sources.list b/src/pcie/sources.list new file mode 100644 index 0000000..d5d95ec --- /dev/null +++ b/src/pcie/sources.list @@ -0,0 +1,9 @@ +src/pcie/regs/verilator.vlt + +src/pcie/regs/pcie_dma_regs_pkg.sv +src/pcie/regs/pcie_dma_regs.sv +src/pcie/regs/pcie_top_regs_pkg.sv +src/pcie/regs/pcie_top_regs.sv + +pcie_dma_wrapper.sv +pcie_top.sv \ No newline at end of file diff --git a/src/regs/alibaba_pcie_top_regs.sv b/src/regs/alibaba_pcie_top_regs.sv index 8269a7b..1b195bc 100644 --- a/src/regs/alibaba_pcie_top_regs.sv +++ b/src/regs/alibaba_pcie_top_regs.sv @@ -11,42 +11,9 @@ module alibaba_pcie_top_regs ( - input logic s_apb_PCLK, - input logic s_apb_PRESETn, - input logic s_apb_PSEL, - input logic s_apb_PENABLE, - input logic s_apb_PWRITE, - input logic [8:0] s_apb_PADDR, - input logic [2:0] s_apb_PPROT, - input logic [31:0] s_apb_PWDATA, - input logic [3:0] s_apb_PSTRB, - output logic [31:0] s_apb_PRDATA, - output logic s_apb_PREADY, - output logic s_apb_PSLVERR, - output logic m_apb_pcie_top_regs_PCLK, - output logic m_apb_pcie_top_regs_PRESETn, - output logic m_apb_pcie_top_regs_PSEL, - output logic m_apb_pcie_top_regs_PENABLE, - output logic m_apb_pcie_top_regs_PWRITE, - output logic [5:0] m_apb_pcie_top_regs_PADDR, - output logic [2:0] m_apb_pcie_top_regs_PPROT, - output logic [31:0] m_apb_pcie_top_regs_PWDATA, - output logic [3:0] m_apb_pcie_top_regs_PSTRB, - input logic [31:0] m_apb_pcie_top_regs_PRDATA, - input logic m_apb_pcie_top_regs_PREADY, - input logic m_apb_pcie_top_regs_PSLVERR, - output logic m_apb_eth_dma_wrapper_regs_PCLK, - output logic m_apb_eth_dma_wrapper_regs_PRESETn, - output logic m_apb_eth_dma_wrapper_regs_PSEL, - output logic m_apb_eth_dma_wrapper_regs_PENABLE, - output logic m_apb_eth_dma_wrapper_regs_PWRITE, - output logic [7:0] m_apb_eth_dma_wrapper_regs_PADDR, - output logic [2:0] m_apb_eth_dma_wrapper_regs_PPROT, - output logic [31:0] m_apb_eth_dma_wrapper_regs_PWDATA, - output logic [3:0] m_apb_eth_dma_wrapper_regs_PSTRB, - input logic [31:0] m_apb_eth_dma_wrapper_regs_PRDATA, - input logic m_apb_eth_dma_wrapper_regs_PREADY, - input logic m_apb_eth_dma_wrapper_regs_PSLVERR + taxi_apb_if.slv s_apb, + taxi_apb_if.mst m_apb_pcie_top_regs, + taxi_apb_if.mst m_apb_eth_dma_wrapper_regs ); //-------------------------------------------------------------------------- // CPU Bus interface logic @@ -81,38 +48,53 @@ module alibaba_pcie_top_regs ( // Slave <-> Internal CPUIF <-> Master //-------------------------------------------------------------------------- + `ifndef SYNTHESIS + initial begin + assert_bad_addr_width: assert($bits(s_apb.paddr) >= alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH) + else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH); + assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH) + else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH); + end + assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr)) + else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded"); + `endif - assign cpuif_req = s_apb_PSEL; - assign cpuif_wr_en = s_apb_PWRITE; - assign cpuif_rd_en = !s_apb_PWRITE; + assign cpuif_req = s_apb.psel; + assign cpuif_wr_en = s_apb.pwrite; + assign cpuif_rd_en = !s_apb.pwrite; - assign cpuif_wr_addr = s_apb_PADDR; - assign cpuif_rd_addr = s_apb_PADDR; + assign cpuif_wr_addr = s_apb.paddr; + assign cpuif_rd_addr = s_apb.paddr; - assign cpuif_wr_data = s_apb_PWDATA; - assign cpuif_wr_byte_en = s_apb_PSTRB; + assign cpuif_wr_data = s_apb.pwdata; + assign cpuif_wr_byte_en = s_apb.pstrb; - assign s_apb_PRDATA = cpuif_rd_data; - assign s_apb_PREADY = cpuif_rd_ack; - assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; + assign s_apb.prdata = cpuif_rd_data; + assign s_apb.pready = cpuif_rd_ack; + assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err; //-------------------------------------------------------------------------- // Fanout CPU Bus interface signals //-------------------------------------------------------------------------- - assign m_apb_pcie_top_regs_PSEL = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs; - assign m_apb_pcie_top_regs_PENABLE = s_apb_PENABLE; - assign m_apb_pcie_top_regs_PWRITE = cpuif_wr_sel.pcie_top_regs; - assign m_apb_pcie_top_regs_PADDR = s_apb_PADDR[5:0]; - assign m_apb_pcie_top_regs_PPROT = s_apb_PPROT; - assign m_apb_pcie_top_regs_PWDATA = cpuif_wr_data; - assign m_apb_pcie_top_regs_PSTRB = cpuif_wr_byte_en; - assign m_apb_eth_dma_wrapper_regs_PSEL = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs; - assign m_apb_eth_dma_wrapper_regs_PENABLE = s_apb_PENABLE; - assign m_apb_eth_dma_wrapper_regs_PWRITE = cpuif_wr_sel.eth_dma_wrapper_regs; - assign m_apb_eth_dma_wrapper_regs_PADDR = s_apb_PADDR[7:0]; - assign m_apb_eth_dma_wrapper_regs_PPROT = s_apb_PPROT; - assign m_apb_eth_dma_wrapper_regs_PWDATA = cpuif_wr_data; - assign m_apb_eth_dma_wrapper_regs_PSTRB = cpuif_wr_byte_en; + assign m_apb_pcie_top_regs.psel = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs; + assign m_apb_pcie_top_regs.penable = s_apb.penable; + assign m_apb_pcie_top_regs.pwrite = cpuif_wr_sel.pcie_top_regs; + assign m_apb_pcie_top_regs.paddr = s_apb.paddr; + assign m_apb_pcie_top_regs.pprot = s_apb.pprot; + assign m_apb_pcie_top_regs.pwdata = cpuif_wr_data; + assign m_apb_pcie_top_regs.pstrb = cpuif_wr_byte_en; + assign m_apb_eth_dma_wrapper_regs.psel = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs; + assign m_apb_eth_dma_wrapper_regs.penable = s_apb.penable; + assign m_apb_eth_dma_wrapper_regs.pwrite = cpuif_wr_sel.eth_dma_wrapper_regs; + assign m_apb_eth_dma_wrapper_regs.paddr = s_apb.paddr; + assign m_apb_eth_dma_wrapper_regs.pprot = s_apb.pprot; + assign m_apb_eth_dma_wrapper_regs.pwdata = cpuif_wr_data; + assign m_apb_eth_dma_wrapper_regs.pstrb = cpuif_wr_byte_en; + + //-------------------------------------------------------------------------- + // Intermediate signals for interface array fanin + //-------------------------------------------------------------------------- + //-------------------------------------------------------------------------- // Fanin CPU Bus interface signals @@ -122,18 +104,18 @@ module alibaba_pcie_top_regs ( cpuif_rd_err = '0; cpuif_rd_data = '0; if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin - cpuif_rd_ack = m_apb_pcie_top_regs_PREADY; - cpuif_rd_err = m_apb_pcie_top_regs_PSLVERR; + cpuif_rd_ack = m_apb_pcie_top_regs.pready; + cpuif_rd_err = m_apb_pcie_top_regs.pslverr; end if (cpuif_rd_sel.pcie_top_regs) begin - cpuif_rd_data = m_apb_pcie_top_regs_PRDATA; + cpuif_rd_data = m_apb_pcie_top_regs.prdata; end if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin - cpuif_rd_ack = m_apb_eth_dma_wrapper_regs_PREADY; - cpuif_rd_err = m_apb_eth_dma_wrapper_regs_PSLVERR; + cpuif_rd_ack = m_apb_eth_dma_wrapper_regs.pready; + cpuif_rd_err = m_apb_eth_dma_wrapper_regs.pslverr; end if (cpuif_rd_sel.eth_dma_wrapper_regs) begin - cpuif_rd_data = m_apb_eth_dma_wrapper_regs_PRDATA; + cpuif_rd_data = m_apb_eth_dma_wrapper_regs.prdata; end end diff --git a/src/regs/compile_regs.sh b/src/regs/compile_regs.sh index 1b9456a..c923d1e 100755 --- a/src/regs/compile_regs.sh +++ b/src/regs/compile_regs.sh @@ -1,4 +1,3 @@ SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl" -peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif apb4-flat -peakrdl c-header -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.h \ No newline at end of file +peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb \ No newline at end of file