From d32d31cead63abbc83ab8a0bde1e3e4cdafa7fd0 Mon Sep 17 00:00:00 2001
From: Byron Lathi <bslathi19@gmail.com>
Date: Sat, 15 Nov 2025 15:42:09 -0800
Subject: [PATCH] Add basic tb that shows it kind of works

---
 sim/alibaba_pcie.py | 67 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 62 insertions(+), 5 deletions(-)

diff --git a/sim/alibaba_pcie.py b/sim/alibaba_pcie.py
index faa7cf9..523bab1 100644
--- a/sim/alibaba_pcie.py
+++ b/sim/alibaba_pcie.py
@@ -8,6 +8,8 @@ from cocotbext.axi import AxiStreamBus
 from cocotbext.pcie.core import RootComplex
 from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
 
+from baser import BaseRSerdesSource, BaseRSerdesSink
+
 CLK_PERIOD = 4
 
 class TB:
@@ -88,12 +90,47 @@ class TB:
 
         self.rc.make_port().connect(self.dev)
 
+        cocotb.start_soon(Clock(dut.sfp_mgt_clk_p, 6.4, units="ns").start())
+
+        self.serdes_sources = []
+        self.serdes_sinks = []
+
+        for ch in dut.u_eth_dma_wrapper.u_taxi_eth_phy_25g_us.ch:
+            gt_inst = ch.ch_inst.gt.gt_inst
+
+            clk = 2.56
+            gbx_cfg = None
+
+            cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
+            cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
+
+            self.serdes_sources.append(BaseRSerdesSource(
+                data=gt_inst.serdes_rx_data,
+                data_valid=gt_inst.serdes_rx_data_valid,
+                hdr=gt_inst.serdes_rx_hdr,
+                hdr_valid=gt_inst.serdes_rx_hdr_valid,
+                clock=gt_inst.rx_clk,
+                slip=gt_inst.serdes_rx_bitslip,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+            self.serdes_sinks.append(BaseRSerdesSink(
+                data=gt_inst.serdes_tx_data,
+                data_valid=gt_inst.serdes_tx_data_valid,
+                hdr=gt_inst.serdes_tx_hdr,
+                hdr_valid=gt_inst.serdes_tx_hdr_valid,
+                gbx_sync=gt_inst.serdes_tx_gbx_sync,
+                clock=gt_inst.tx_clk,
+                reverse=True,
+                gbx_cfg=gbx_cfg
+            ))
+
 @cocotb.test
 async def test_sanity(dut):
     tb = TB(dut)
 
     await FallingEdge(dut.rst_250)
-    await Timer(100, 'ns')
+    await Timer(10, 'us')
 
     await tb.rc.enumerate()
 
@@ -117,7 +154,27 @@ async def test_sanity(dut):
     await dev_bar0.write_dword(0xc, len(message))
     await dev_bar0.write_dword(0x10, 0x00000001)
 
-    await Timer(100, "ns")
+    await Timer(1, "us")
+
+    await dev_bar0.write_dword(0x40, 0x00000000)
+    await dev_bar0.write_dword(0x44, 0x00000000)
+    await dev_bar0.write_dword(0x48, 0x00000000)
+    await dev_bar0.write_dword(0x4c, len(message))
+    await dev_bar0.write_dword(0x50, 0x00000001)
+
+    await dev_bar0.write_dword(0x60, 0x00000000)
+    await dev_bar0.write_dword(0x64, 0x00000000)
+    await dev_bar0.write_dword(0x68, 0x00000000)
+    await dev_bar0.write_dword(0x6c, len(message))
+    await dev_bar0.write_dword(0x70, 0x00000001)
+
+    rx_frame = await tb.serdes_sinks[0].recv()
+
+    tb.log.info(rx_frame)
+
+    await tb.serdes_sources[1].send(rx_frame)
+
+    await Timer(1, "us")
 
     await dev_bar0.write_dword(0x20, 0x00000100)
     await dev_bar0.write_dword(0x24, 0x00000000)
@@ -125,8 +182,8 @@ async def test_sanity(dut):
     await dev_bar0.write_dword(0x2c, len(message))
     await dev_bar0.write_dword(0x30, 0x00000001)
 
-    await Timer(10, "us")
+    await Timer(1, "us")
 
-    read_msg = await mem.read(0x100, len(message))
+    msg = await mem.read(0x100, len(message))
 
-    tb.log.info(read_msg)
\ No newline at end of file
+    tb.log.info(msg)
\ No newline at end of file