bslathi19/alibaba_pcie
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Get it kind of working again

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This commit is contained in:
Byron Lathi
2025-11-22 17:02:25 -08:00
parent 85cb3cc2a6
commit d9a25d0a7a
13 changed files with 58 additions and 38 deletions
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4
src/pcie/regs/pcie_top_regs.sv
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@@ -53,8 +53,10 @@ module pcie_top_regs (
assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb.psel;
@@ -65,7 +67,7 @@ module pcie_top_regs (
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.PSTRB;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;