Get it kind of working again

src/regs/alibaba_pcie_top_regs.sv

@@ -55,8 +55,10 @@ module alibaba_pcie_top_regs (
             assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH)
                 else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH);
         end
+        `ifdef PEAKRDL_ASSERTIONS
         assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
             else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
     `endif
 
     assign cpuif_req   = s_apb.psel;

src/regs/verilator.vlt

@@ -0,0 +1,4 @@
+`verilator_config
+
+lint_off -rule MULTIDRIVEN -file "**/regs/*"
+lint_off -file "**/regs/*"