Get it kind of working again

requirements.txt

@@ -7,4 +7,4 @@ rtl-manifest
 build_fpga
 fpga-sim
 peakrdl
-git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@dev/taxi_apb
+git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb

sim/alibaba_pcie.py

@@ -78,12 +78,12 @@ class TB:
             # signals
             user_clk=dut.clk_250,
             user_reset=dut.rst_250,
-            user_lnk_up=dut.user_lnk_up,
+            user_lnk_up=dut.u_pcie_top.user_lnk_up,
 
-            rq_bus=AxiStreamBus.from_entity(dut.s_axis_rq),
+            rq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_rq),
-            rc_bus=AxiStreamBus.from_entity(dut.m_axis_rc),
+            rc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_rc),
-            cq_bus=AxiStreamBus.from_entity(dut.m_axis_cq),
+            cq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_cq),
-            cc_bus=AxiStreamBus.from_entity(dut.s_axis_cc),
+            cc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_cc),
         )
 
         self.dev.functions[0].configure_bar(0, 64*1024)
@@ -142,8 +142,6 @@ async def test_sanity(dut):
 
     dev_bar0 = dev.bar_window[0]
 
-    tb.log.info(dev_bar0.write)
-
     message = b"Hello, world! This is a long string of data with many letters and words."
 
     await mem.write(0, message)

sources.list

@@ -6,8 +6,8 @@ ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci
 
 sub/taxi_sources.list
 
-eth/sources.list
+src/pcie/sources.list
-pcie/sources.list
+src/eth/sources.list
 
 src/regs/verilator.vlt
 src/regs/alibaba_pcie_top_regs_pkg.sv

src/alibaba_pcie_top.sv

@@ -42,6 +42,8 @@ module alibaba_pcie(
 );
 
 
+logic clk_250;
+logic rst_250;
 
 taxi_axil_if m_axil_rd();
 taxi_axil_if m_axil_wr();
@@ -90,10 +92,10 @@ eth_dma_wrapper u_eth_dma_wrapper (
 );
 
 pcie_top u_pcie_top(
-    .pcie_exp_rxp       (pcie_exp_rxp)
+    .pci_exp_rxp        (pci_exp_rxp),
-    .pcie_exp_rxn       (pcie_exp_rxn)
+    .pci_exp_rxn        (pci_exp_rxn),
-    .pcie_exp_txp       (pcie_exp_txp)
+    .pci_exp_txp        (pci_exp_txp),
-    .pcie_exp_txn       (pcie_exp_txn),
+    .pci_exp_txn        (pci_exp_txn),
 
     .pcie_mgt_refclk_p  (pcie_mgt_refclk_p),
     .pcie_mgt_refclk_n  (pcie_mgt_refclk_n),
@@ -103,6 +105,9 @@ pcie_top u_pcie_top(
     .user_lnk_up        (Led_o[0]),
     .phy_rdy_out        (Led_o[1]),
 
+    .o_clk_250          (clk_250),
+    .o_rst_250          (rst_250),
+
     .dma_ram_eth_wr_if  (dma_ram_eth_wr_if),
     .dma_ram_eth_rd_if  (dma_ram_eth_rd_if),
 

src/eth/eth_dma_wrapper.sv

@@ -84,7 +84,7 @@ endgenerate
 
 taxi_axis_if axis_sfp_stat();
 
-taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
+taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
 taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb();
 
 
@@ -105,19 +105,23 @@ eth_mac_25g_us_regs u_eth_mac_25g_us_regs (
     .s_apb_prdata                   (eth_mac_apb.prdata),
     .s_apb_pslverr                  (eth_mac_apb.pslverr),
 
-    .hwif_in                        (hwif_in),
+    .hwif_in                        (hwif_in)
-    .hwif_out                       (hwif_out)
 );
 
-assign hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
-
 logic rx_block_lock[2];
 logic rx_status[2];
 
+logic xcvr_qpll0lock_out;
+logic xcvr_qpll1lock_out;
+
 always_comb begin
+    hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
+    hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next = xcvr_qpll0lock_out;
+    hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next = xcvr_qpll1lock_out;
+
     for (int i = 0; i < 2; i++) begin
-        assign hwif_in.lane[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
+        hwif_in.lanes[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
-        assign hwif_in.lane[i].rx_status.rx_status.next = rx_status[i];
+        hwif_in.lanes[i].rx_status.rx_status.next = rx_status[i];
     end
 end
 
@@ -144,14 +148,14 @@ taxi_eth_mac_25g_us #(
     .xcvr_qpll0pd_in                    (1'b0),
     .xcvr_qpll0reset_in                 (1'b0),
     .xcvr_qpll0pcierate_in              (3'd0),
-    .xcvr_qpll0lock_out                 (hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next),
+    .xcvr_qpll0lock_out                 (xcvr_qpll0lock_out),
     .xcvr_qpll0clk_out                  (),
     .xcvr_qpll0refclk_out               (),
     .xcvr_gtrefclk01_in                 (sfp_mgt_refclk),
     .xcvr_qpll1pd_in                    (1'b0),
     .xcvr_qpll1reset_in                 (1'b0),
     .xcvr_qpll1pcierate_in              (3'd0),
-    .xcvr_qpll1lock_out                 (hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next),
+    .xcvr_qpll1lock_out                 (xcvr_qpll1lock_out),
     .xcvr_qpll1clk_out                  (),
     .xcvr_qpll1refclk_out               (),
 

src/eth/regs/eth_dma_wrapper_regs.sv

@@ -55,8 +55,10 @@ module eth_dma_wrapper_regs (
             assert_bad_data_width: assert($bits(s_apb.pwdata) == eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH)
                 else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH);
         end
+        `ifdef PEAKRDL_ASSERTIONS
         assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
             else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
     `endif
 
     assign cpuif_req   = s_apb.psel;
@@ -67,7 +69,7 @@ module eth_dma_wrapper_regs (
     assign cpuif_rd_addr = s_apb.paddr;
 
     assign cpuif_wr_data = s_apb.pwdata;
-    assign cpuif_wr_byte_en = s_apb.PSTRB;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
 
     assign s_apb.prdata = cpuif_rd_data;
     assign s_apb.pready = cpuif_rd_ack;

src/eth/sources.list

@@ -1,6 +1,6 @@
-src/eth/regs/eth_dma_wrapper_regs_pkg.sv
+regs/eth_dma_wrapper_regs_pkg.sv
-src/eth/regs/eth_dma_wrapper_regs.sv
+regs/eth_dma_wrapper_regs.sv
-src/eth/regs/eth_mac_25g_us_regs_pkg.sv
+regs/eth_mac_25g_us_regs_pkg.sv
-src/eth/regs/eth_mac_25g_us_regs.sv
+regs/eth_mac_25g_us_regs.sv
 
 eth_dma_wrapper.sv

src/pcie/pcie_top.sv

@@ -12,6 +12,9 @@ module pcie_top(
     output wire                     user_lnk_up,
     output wire                     phy_rdy_out,
 
+    output wire                     o_clk_250,
+    output wire                     o_rst_250,
+
     taxi_dma_ram_if.wr_slv          dma_ram_eth_wr_if,
     taxi_dma_ram_if.rd_slv          dma_ram_eth_rd_if,
 
@@ -29,8 +32,8 @@ logic rst_pcie;
 logic clk_250;
 logic rst_250;
 
-logic user_lnk_up;
+assign o_clk_250 = clk_250;
-logic phy_rdy_out;
+assign o_rst_250 = rst_250;
 
 taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
 taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
@@ -57,7 +60,7 @@ IBUFDS_GTE4 m_ibufds (
 pcie_top_regs u_pcie_top_regs (
     .s_apb              (s_apb),
     .m_apb_pcie_dma_regs(pcie_dma_apb)
-)
+);
 
 taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
     .clk                (clk_250),

src/pcie/regs/pcie_top_regs.sv

@@ -53,8 +53,10 @@ module pcie_top_regs (
             assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
                 else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
         end
+        `ifdef PEAKRDL_ASSERTIONS
         assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
             else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
     `endif
 
     assign cpuif_req   = s_apb.psel;
@@ -65,7 +67,7 @@ module pcie_top_regs (
     assign cpuif_rd_addr = s_apb.paddr;
 
     assign cpuif_wr_data = s_apb.pwdata;
-    assign cpuif_wr_byte_en = s_apb.PSTRB;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
 
     assign s_apb.prdata = cpuif_rd_data;
     assign s_apb.pready = cpuif_rd_ack;

src/pcie/sources.list

@@ -1,9 +1,9 @@
-src/pcie/regs/verilator.vlt
+regs/verilator.vlt
 
-src/pcie/regs/pcie_dma_regs_pkg.sv
+regs/pcie_dma_regs_pkg.sv
-src/pcie/regs/pcie_dma_regs.sv
+regs/pcie_dma_regs.sv
-src/pcie/regs/pcie_top_regs_pkg.sv
+regs/pcie_top_regs_pkg.sv
-src/pcie/regs/pcie_top_regs.sv
+regs/pcie_top_regs.sv
 
 pcie_dma_wrapper.sv
 pcie_top.sv

src/regs/alibaba_pcie_top_regs.sv

@@ -55,8 +55,10 @@ module alibaba_pcie_top_regs (
             assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH)
                 else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH);
         end
+        `ifdef PEAKRDL_ASSERTIONS
         assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
             else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
     `endif
 
     assign cpuif_req   = s_apb.psel;

src/regs/verilator.vlt

@@ -0,0 +1,4 @@
+`verilator_config
+
+lint_off -rule MULTIDRIVEN -file "**/regs/*"
+lint_off -file "**/regs/*"