Add more register printout

requirements.txt

@@ -7,4 +7,5 @@ rtl-manifest
 build_fpga
 fpga-sim
 peakrdl
+peakrdl-python-regmap
 git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb

sim/alibaba_pcie.py

@@ -10,6 +10,8 @@ from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
 
 from baser import BaseRSerdesSource, BaseRSerdesSink
 
+from alibaba_pcie_top_regs import alibaba_pcie_top_regsClass
+
 CLK_PERIOD = 4
 
 class TB:
@@ -76,8 +78,8 @@ class TB:
             pf3_msix_pba_offset=0x00000000,
 
             # signals
-            user_clk=dut.clk_250,
-            user_reset=dut.rst_250,
+            user_clk=dut.u_pcie_top.clk_250,
+            user_reset=dut.u_pcie_top.rst_250,
             user_lnk_up=dut.u_pcie_top.user_lnk_up,
 
             rq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_rq),
@@ -146,25 +148,36 @@ async def test_sanity(dut):
 
     await mem.write(0, message)
 
-    await dev_bar0.write_dword(0x0, 0x00000000)
-    await dev_bar0.write_dword(0x4, 0x00000000)
-    await dev_bar0.write_dword(0x8, 0x00000000)
-    await dev_bar0.write_dword(0xc, len(message))
-    await dev_bar0.write_dword(0x10, 0x00000001)
+    regmap = alibaba_pcie_top_regsClass()
+    pcie_dma_rd = regmap.pcie_top_regs.pcie_dma_regs.dma_rd
+    pcie_dma_wr = regmap.pcie_top_regs.pcie_dma_regs.dma_wr
+
+    eth_dma_rd = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_rd
+    eth_dma_wr = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_wr
+
+
+    # DMA from host to dma memory
+    await dev_bar0.write_dword(pcie_dma_rd.src_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.src_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.dst_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.length.addr, len(message))
+    await dev_bar0.write_dword(pcie_dma_rd.trigger.addr, 0x00000001)
 
     await Timer(1, "us")
 
-    await dev_bar0.write_dword(0x40, 0x00000000)
-    await dev_bar0.write_dword(0x44, 0x00000000)
-    await dev_bar0.write_dword(0x48, 0x00000000)
-    await dev_bar0.write_dword(0x4c, len(message))
-    await dev_bar0.write_dword(0x50, 0x00000001)
+    # Set up stream to memory DMA to store ethernet frame
+    await dev_bar0.write_dword(eth_dma_wr.src_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.dst_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.dst_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.length.addr, len(message))
+    await dev_bar0.write_dword(eth_dma_wr.trigger.addr, 0x00000001)
 
-    await dev_bar0.write_dword(0x60, 0x00000000)
-    await dev_bar0.write_dword(0x64, 0x00000000)
-    await dev_bar0.write_dword(0x68, 0x00000000)
-    await dev_bar0.write_dword(0x6c, len(message))
-    await dev_bar0.write_dword(0x70, 0x00000001)
+    # Trigger memory to stream dma to send ethernet frame
+    await dev_bar0.write_dword(eth_dma_rd.src_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.src_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.dst_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.length.addr, len(message))
+    await dev_bar0.write_dword(eth_dma_rd.trigger.addr, 0x00000001)
 
     rx_frame = await tb.serdes_sinks[0].recv()
 
@@ -174,11 +187,12 @@ async def test_sanity(dut):
 
     await Timer(1, "us")
 
-    await dev_bar0.write_dword(0x20, 0x00000100)
-    await dev_bar0.write_dword(0x24, 0x00000000)
-    await dev_bar0.write_dword(0x28, 0x00000000)
-    await dev_bar0.write_dword(0x2c, len(message))
-    await dev_bar0.write_dword(0x30, 0x00000001)
+    # DMA from dma memory to host
+    await dev_bar0.write_dword(pcie_dma_wr.src_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.dst_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.dst_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.length.addr, len(message))
+    await dev_bar0.write_dword(pcie_dma_wr.trigger.addr, 0x00000001)
 
     await Timer(1, "us")
 

sim/alibaba_pcie_top_regs.py

@@ -0,0 +1 @@
+../src/regs/alibaba_pcie_top_regs.py

src/eth/eth_dma_wrapper.sv

@@ -87,6 +87,11 @@ taxi_axis_if axis_sfp_stat();
 taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
 taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb();
 
+eth_dma_wrapper_regs u_eth_dma_wrapper_regs (
+    .s_apb                          (s_apb),
+    .m_apb_eth_mac_25g_us_regs      (eth_mac_apb),
+    .m_apb_pcie_dma_regs            (eth_dma_apb)
+);
 
 eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in;
 

src/regs/alibaba_pcie_top_regs.py

@@ -0,0 +1,165 @@
+class AddrNode():
+    addr: int
+class alibaba_pcie_top_regsClass(AddrNode):
+    class pcie_top_regsClass(AddrNode):
+        class pcie_dma_regsClass(AddrNode):
+            class dma_rdClass(AddrNode):
+                class src_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
+                    self.src_addr_high = self.src_addr_highClass(self.addr + 4)
+                    self.dst_addr = self.dst_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            class dma_wrClass(AddrNode):
+                class dst_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
+                    self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
+                    self.src_addr = self.src_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.dma_rd = self.dma_rdClass(self.addr + 0)
+                self.dma_wr = self.dma_wrClass(self.addr + 32)
+        def __init__(self, addr: int = 0):
+            self.addr = addr
+            self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 0)
+    class eth_dma_wrapper_regsClass(AddrNode):
+        class eth_mac_25g_us_regsClass(AddrNode):
+            class commonClass(AddrNode):
+                class xcvr_gtpowergood_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class xcvr_qpll0lock_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class xcvr_qpll1lock_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.xcvr_gtpowergood_out = self.xcvr_gtpowergood_outClass(self.addr + 0)
+                    self.xcvr_qpll0lock_out = self.xcvr_qpll0lock_outClass(self.addr + 4)
+                    self.xcvr_qpll1lock_out = self.xcvr_qpll1lock_outClass(self.addr + 8)
+            class lanesClass(AddrNode):
+                class rx_block_lockClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class rx_statusClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.rx_block_lock = self.rx_block_lockClass(self.addr + 0)
+                    self.rx_status = self.rx_statusClass(self.addr + 4)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.common = self.commonClass(self.addr + 0)
+                self.lanes = [self.lanesClass(self.addr + 32 + 8*i) for i in range(2)]
+        class pcie_dma_regsClass(AddrNode):
+            class dma_rdClass(AddrNode):
+                class src_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
+                    self.src_addr_high = self.src_addr_highClass(self.addr + 4)
+                    self.dst_addr = self.dst_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            class dma_wrClass(AddrNode):
+                class dst_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
+                    self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
+                    self.src_addr = self.src_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.dma_rd = self.dma_rdClass(self.addr + 0)
+                self.dma_wr = self.dma_wrClass(self.addr + 32)
+        def __init__(self, addr: int = 0):
+            self.addr = addr
+            self.eth_mac_25g_us_regs = self.eth_mac_25g_us_regsClass(self.addr + 0)
+            self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 128)
+    def __init__(self, addr: int = 0):
+        self.addr = addr
+        self.pcie_top_regs = self.pcie_top_regsClass(self.addr + 0)
+        self.eth_dma_wrapper_regs = self.eth_dma_wrapper_regsClass(self.addr + 256)

src/regs/alibaba_pcie_top_regs.sv

@@ -3,8 +3,8 @@
 //  Description: CPU Interface Bus Decoder
 //  Author: PeakRDL-BusDecoder
 //  License: LGPL-3.0
-//  Date: 2025-11-22
-//  Version: 0.5.0
+//  Date: 2025-11-23
+//  Version: 0.6.0
 //  Links:
 //    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
 //==========================================================

src/regs/alibaba_pcie_top_regs_pkg.sv

@@ -3,8 +3,8 @@
 //  Description: CPU Interface Bus Decoder Package
 //  Author: PeakRDL-BusDecoder
 //  License: LGPL-3.0
-//  Date: 2025-11-22
-//  Version: 0.5.0
+//  Date: 2025-11-23
+//  Version: 0.6.0
 //  Links:
 //    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
 //==========================================================

src/regs/compile_regs.sh

@@ -1,3 +1,6 @@
 SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
 
-peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb
+peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb
+peakrdl python-regmap -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.py
+peakrdl html -t alibaba_pcie_top_regs $SRCS -o html
+peakrdl c-header -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.h

sw/test/alibaba_pcie_top_regs.h

@@ -0,0 +1 @@
+../../src/regs/alibaba_pcie_top_regs.h

sw/test/pcie_dma_test.c

@@ -7,6 +7,8 @@
 #include <sys/mman.h>
 #include <string.h>
 
+#include "alibaba_pcie_top_regs.h"
+
 typedef struct {
     uint64_t pfn : 55;
     unsigned int soft_dirty : 1;
@@ -105,8 +107,8 @@ int main(void)
     // this is hardcoded, seems to be deterministic.
     uint32_t pcie_physical_base_offset = 0xfe800000;
     int fd = open("/dev/mem", O_RDWR|O_SYNC);
-    uint32_t* pcie_base = (uint32_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
-    printf("Virtual PCIe Base: %p\n", pcie_base);
+    alibaba_pcie_top_regs_t* top_regs = (alibaba_pcie_top_regs_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
+    printf("Virtual PCIe Base: %p\n", top_regs);
 
 
     for (int i = 0; i < 2; i++) { 
@@ -119,34 +121,60 @@ int main(void)
         memset((void*)dst, 0, 1024);
 
         printf("Sending read DMA\n");
-        pcie_base[0] = (uint32_t)src_phys;
-        pcie_base[1] = (uint32_t)(src_phys >> 32);
-        pcie_base[2] = dma_mem_addr;
-        pcie_base[3] = strlen(src);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_low = (uint32_t)src_phys;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_high = (uint32_t)(src_phys >> 32);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.dst_addr = dma_mem_addr;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.length = strlen(src);
 
         for (int i = 0; i < 4; i++) {
-            printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
+            printf("pcie_rd_dma[%d] = %x\n", i, (&top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_low)[i]);
         }
 
-        pcie_base[4] = 1;
-        printf("%d\n", pcie_base[4]);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.trigger = 1;
+        printf("%d\n", top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.trigger);
         printf("\n\n");
 
         printf("Sending write DMA\n");
 
+        // we use dma_mem_addr twice, but these are actually 2 separate memories.
 
-        printf("Sending read DMA\n");
-        pcie_base[8] = (uint32_t)dst_phys;
-        pcie_base[9] = (uint32_t)(dst_phys >> 32);
-        pcie_base[10] = dma_mem_addr;
-        pcie_base[11] = strlen(src);
+        // Set up stream to memory DMA to store ethernet frame
+        printf("Setting up stream to memory DMA\n");
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.src_addr = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_low = dma_mem_addr;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_high =  0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.length = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.trigger = 1;
 
-        for (int i = 8; i < 12; i++) {
-            printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
+        for (int i = 0; i < 4; i++) {
+            printf("eth_wr_dma[%d] = %x\n", i, (&top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_low )[i]);
         }
 
-        pcie_base[12] = 1;
-        printf("%d\n", pcie_base[12]);
+        // Trigger memory to stream dma to send ethernet frame
+        printf("Sending memory to stream DMA\n");
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_low = dma_mem_addr;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_high = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.dst_addr = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.length = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.trigger = 1;
+
+        for (int i = 0; i < 4; i++) {
+            printf("eth_rd_dma[%d] = %x\n", i, (&top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_low)[i]);
+        }
+
+
+        printf("Sending read DMA\n");
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_low = (uint32_t)dst_phys;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_high = (uint32_t)(dst_phys >> 32);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.src_addr = dma_mem_addr;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.length = strlen(src);
+
+        for (int i = 8; i < 12; i++) {
+            printf("pcie_wr_dma[%d] = %x\n", i, (&top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_low)[i]);
+        }
+
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.trigger = 1;
+        printf("%d\n", top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.trigger);
         printf("\n\n");
 
         printf("strlen(dst)=%d\n", strlen(dst));