# Global clock signal set_property -dict {LOC E18 IOSTANDARD LVDS} [get_ports Clk_100mhz_p_i] set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports Clk_100mhz_n_i] create_clock -period 10 -name clk_100mhz [get_ports Clk_100mhz_p_i] set_property -dict {LOC T7} [get_ports pcie_mgt_refclk_p] set_property -dict {LOC T6} [get_ports pcie_mgt_refclk_n] create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p] create_clock -period 4 -name clk_250 # LEDS set_property -dict {LOC B11 IOSTANDARD LVCMOS18} [get_ports { Led_o[0]}] set_property -dict {LOC C11 IOSTANDARD LVCMOS18} [get_ports { Led_o[1]}] set_property -dict {LOC A10 IOSTANDARD LVCMOS18} [get_ports { Led_o[2]}] set_property -dict {LOC B10 IOSTANDARD LVCMOS18} [get_ports { Led_o[3]}] set_property -dict {LOC R4} [get_ports {pci_exp_txn[0]}] set_property -dict {LOC U4} [get_ports {pci_exp_txn[1]}] set_property -dict {LOC W4} [get_ports {pci_exp_txn[2]}] set_property -dict {LOC AA4} [get_ports {pci_exp_txn[3]}] set_property -dict {LOC AC4} [get_ports {pci_exp_txn[4]}] set_property -dict {LOC AD6} [get_ports {pci_exp_txn[5]}] set_property -dict {LOC AE8} [get_ports {pci_exp_txn[6]}] set_property -dict {LOC AF6} [get_ports {pci_exp_txn[7]}] set_property -dict {LOC P1} [get_ports {pci_exp_rxn[0]}] set_property -dict {LOC T1} [get_ports {pci_exp_rxn[1]}] set_property -dict {LOC V1} [get_ports {pci_exp_rxn[2]}] set_property -dict {LOC Y1} [get_ports {pci_exp_rxn[3]}] set_property -dict {LOC AB1} [get_ports {pci_exp_rxn[4]}] set_property -dict {LOC AD1} [get_ports {pci_exp_rxn[5]}] set_property -dict {LOC AE3} [get_ports {pci_exp_rxn[6]}] set_property -dict {LOC AF1} [get_ports {pci_exp_rxn[7]}] set_property -dict {LOC R5} [get_ports {pci_exp_txp[0]}] set_property -dict {LOC U5} [get_ports {pci_exp_txp[1]}] set_property -dict {LOC W5} [get_ports {pci_exp_txp[2]}] set_property -dict {LOC AA5} [get_ports {pci_exp_txp[3]}] set_property -dict {LOC AC5} [get_ports {pci_exp_txp[4]}] set_property -dict {LOC AD7} [get_ports {pci_exp_txp[5]}] set_property -dict {LOC AE9} [get_ports {pci_exp_txp[6]}] set_property -dict {LOC AF7} [get_ports {pci_exp_txp[7]}] set_property -dict {LOC P2} [get_ports {pci_exp_rxp[0]}] set_property -dict {LOC T2} [get_ports {pci_exp_rxp[1]}] set_property -dict {LOC V2} [get_ports {pci_exp_rxp[2]}] set_property -dict {LOC Y2} [get_ports {pci_exp_rxp[3]}] set_property -dict {LOC AB2} [get_ports {pci_exp_rxp[4]}] set_property -dict {LOC AD2} [get_ports {pci_exp_rxp[5]}] set_property -dict {LOC AE4} [get_ports {pci_exp_rxp[6]}] set_property -dict {LOC AF2} [get_ports {pci_exp_rxp[7]}] set_property -dict {LOC B6} [get_ports {sfp_txn[0]}] set_property -dict {LOC B7} [get_ports {sfp_txp[0]}] set_property -dict {LOC A3} [get_ports {sfp_rxn[0]}] set_property -dict {LOC A4} [get_ports {sfp_rxp[0]}] set_property -dict {LOC D6} [get_ports {sfp_txn[1]}] set_property -dict {LOC D7} [get_ports {sfp_txp[1]}] set_property -dict {LOC B1} [get_ports {sfp_rxn[1]}] set_property -dict {LOC B2} [get_ports {sfp_rxp[1]}] set_property -dict {LOC K7} [get_ports {sfp_mgt_clk_p}] set_property -dict {LOC K6} [get_ports {sfp_mgt_clk_n}] set_property -dict {LOC A9 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]