// Generated by PeakRDL-cheader - A free and open-source header generator
//  https://github.com/SystemRDL/PeakRDL-cheader

#ifndef ALIBABA_PCIE_TOP_REGS_H
#define ALIBABA_PCIE_TOP_REGS_H

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>
#include <assert.h>

// Reg - pcie_dma_regs::dma_rd::src_addr_low
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_reset 0x0

// Reg - pcie_dma_regs::dma_rd::src_addr_high
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_reset 0x0

// Reg - pcie_dma_regs::dma_rd::dst_addr
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bm 0xffff
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bw 16
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_reset 0x0

// Reg - pcie_dma_regs::dma_rd::length
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bm 0xffff
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bp 0
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bw 16
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_reset 0x0

// Reg - pcie_dma_regs::dma_rd::trigger
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bm 0x1
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bp 0
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bw 1
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_reset 0x0

// Reg - pcie_dma_regs::dma_rd::done
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bm 0x1
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bp 0
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bw 1
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_reset 0x0

// Regfile - pcie_dma_regs::dma_rd
typedef struct __attribute__ ((__packed__)) {
    uint32_t src_addr_low;
    uint32_t src_addr_high;
    uint32_t dst_addr;
    uint32_t length;
    uint32_t trigger;
    uint32_t done;
} pcie_dma_regs__dma_rd_t;

// Reg - pcie_dma_regs::dma_wr::dst_addr_low
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_reset 0x0

// Reg - pcie_dma_regs::dma_wr::dst_addr_high
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_reset 0x0

// Reg - pcie_dma_regs::dma_wr::src_addr
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bm 0xffff
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bw 16
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_reset 0x0

// Reg - pcie_dma_regs::dma_wr::length
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bm 0xffff
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bp 0
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bw 16
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_reset 0x0

// Reg - pcie_dma_regs::dma_wr::trigger
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bm 0x1
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bp 0
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bw 1
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_reset 0x0

// Reg - pcie_dma_regs::dma_wr::done
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bm 0x1
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bp 0
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bw 1
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_reset 0x0

// Regfile - pcie_dma_regs::dma_wr
typedef struct __attribute__ ((__packed__)) {
    uint32_t dst_addr_low;
    uint32_t dst_addr_high;
    uint32_t src_addr;
    uint32_t length;
    uint32_t trigger;
    uint32_t done;
} pcie_dma_regs__dma_wr_t;

// Addrmap - pcie_dma_regs
typedef struct __attribute__ ((__packed__)) {
    pcie_dma_regs__dma_rd_t dma_rd;
    uint8_t RESERVED_18_1f[0x8];
    pcie_dma_regs__dma_wr_t dma_wr;
} pcie_dma_regs_t;

// Addrmap - pcie_top_regs
typedef struct __attribute__ ((__packed__)) {
    pcie_dma_regs_t pcie_dma_regs;
} pcie_top_regs_t;

// Reg - eth_mac_25g_us_regs::common::xcvr_gtpowergood_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_reset 0x0

// Reg - eth_mac_25g_us_regs::common::xcvr_qpll0lock_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_reset 0x0

// Reg - eth_mac_25g_us_regs::common::xcvr_qpll1lock_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_reset 0x0

// Regfile - eth_mac_25g_us_regs::common
typedef struct __attribute__ ((__packed__)) {
    uint32_t xcvr_gtpowergood_out;
    uint32_t xcvr_qpll0lock_out;
    uint32_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common_t;

// Reg - eth_mac_25g_us_regs::lane::rx_block_lock
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bm 0x1
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bp 0
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bw 1
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_reset 0x0

// Reg - eth_mac_25g_us_regs::lane::rx_status
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bm 0x1
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bp 0
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bw 1
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_reset 0x0

// Regfile - eth_mac_25g_us_regs::lane
typedef struct __attribute__ ((__packed__)) {
    uint32_t rx_block_lock;
    uint32_t rx_status;
    uint8_t RESERVED_8_1f[0x18];
} eth_mac_25g_us_regs__lane__stride20_t;

// Addrmap - eth_mac_25g_us_regs
typedef struct __attribute__ ((__packed__)) {
    eth_mac_25g_us_regs__common_t common;
    uint8_t RESERVED_c_1f[0x14];
    eth_mac_25g_us_regs__lane__stride20_t lanes[2];
} eth_mac_25g_us_regs_t;

// Addrmap - eth_dma_wrapper_regs
typedef struct __attribute__ ((__packed__)) {
    eth_mac_25g_us_regs_t eth_mac_25g_us_regs;
    uint8_t RESERVED_60_7f[0x20];
    pcie_dma_regs_t pcie_dma_regs;
} eth_dma_wrapper_regs_t;

// Addrmap - alibaba_pcie_top_regs
typedef struct __attribute__ ((__packed__)) {
    pcie_top_regs_t pcie_top_regs;
    uint8_t RESERVED_38_ff[0xc8];
    eth_dma_wrapper_regs_t eth_dma_wrapper_regs;
} alibaba_pcie_top_regs_t;


static_assert(sizeof(alibaba_pcie_top_regs_t) == 0x1b8, "Packing error");

#ifdef __cplusplus
}
#endif

#endif /* ALIBABA_PCIE_TOP_REGS_H */