//==========================================================
//  Module: alibaba_pcie_top_regs
//  Description: CPU Interface Bus Decoder
//  Author: PeakRDL-BusDecoder
//  License: LGPL-3.0
//  Date: 2025-11-22
//  Version: 0.5.0
//  Links:
//    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================


module alibaba_pcie_top_regs (
    input  logic s_apb_PCLK,
    input  logic s_apb_PRESETn,
    input  logic s_apb_PSEL,
    input  logic s_apb_PENABLE,
    input  logic s_apb_PWRITE,
    input  logic [8:0] s_apb_PADDR,
    input  logic [2:0] s_apb_PPROT,
    input  logic [31:0] s_apb_PWDATA,
    input  logic [3:0] s_apb_PSTRB,
    output logic [31:0] s_apb_PRDATA,
    output logic s_apb_PREADY,
    output logic s_apb_PSLVERR,
    output logic m_apb_pcie_top_regs_PCLK,
    output logic m_apb_pcie_top_regs_PRESETn,
    output logic m_apb_pcie_top_regs_PSEL,
    output logic m_apb_pcie_top_regs_PENABLE,
    output logic m_apb_pcie_top_regs_PWRITE,
    output logic [5:0] m_apb_pcie_top_regs_PADDR,
    output logic [2:0] m_apb_pcie_top_regs_PPROT,
    output logic [31:0] m_apb_pcie_top_regs_PWDATA,
    output logic [3:0] m_apb_pcie_top_regs_PSTRB,
    input  logic [31:0] m_apb_pcie_top_regs_PRDATA,
    input  logic m_apb_pcie_top_regs_PREADY,
    input  logic m_apb_pcie_top_regs_PSLVERR,
    output logic m_apb_eth_dma_wrapper_regs_PCLK,
    output logic m_apb_eth_dma_wrapper_regs_PRESETn,
    output logic m_apb_eth_dma_wrapper_regs_PSEL,
    output logic m_apb_eth_dma_wrapper_regs_PENABLE,
    output logic m_apb_eth_dma_wrapper_regs_PWRITE,
    output logic [7:0] m_apb_eth_dma_wrapper_regs_PADDR,
    output logic [2:0] m_apb_eth_dma_wrapper_regs_PPROT,
    output logic [31:0] m_apb_eth_dma_wrapper_regs_PWDATA,
    output logic [3:0] m_apb_eth_dma_wrapper_regs_PSTRB,
    input  logic [31:0] m_apb_eth_dma_wrapper_regs_PRDATA,
    input  logic m_apb_eth_dma_wrapper_regs_PREADY,
    input  logic m_apb_eth_dma_wrapper_regs_PSLVERR
);
    //--------------------------------------------------------------------------
    // CPU Bus interface logic
    //--------------------------------------------------------------------------
    logic cpuif_req;
    logic cpuif_wr_en;
    logic cpuif_rd_en;
    logic [8:0] cpuif_wr_addr;
    logic [8:0] cpuif_rd_addr;

    logic cpuif_wr_ack;
    logic cpuif_wr_err;
    logic [31:0] cpuif_wr_data;
    logic [3:0] cpuif_wr_byte_en;

    logic cpuif_rd_ack;
    logic cpuif_rd_err;
    logic [31:0] cpuif_rd_data;

    //--------------------------------------------------------------------------
    // Child instance signals
    //--------------------------------------------------------------------------
    typedef struct {
        logic pcie_top_regs;
        logic eth_dma_wrapper_regs;
        logic cpuif_err;
    } cpuif_sel_t;
    cpuif_sel_t cpuif_wr_sel;
    cpuif_sel_t cpuif_rd_sel;

    //--------------------------------------------------------------------------
    // Slave <-> Internal CPUIF <-> Master
    //--------------------------------------------------------------------------
    

    assign cpuif_req   = s_apb_PSEL;
    assign cpuif_wr_en = s_apb_PWRITE;
    assign cpuif_rd_en = !s_apb_PWRITE;

    assign cpuif_wr_addr = s_apb_PADDR;
    assign cpuif_rd_addr = s_apb_PADDR;

    assign cpuif_wr_data = s_apb_PWDATA;
    assign cpuif_wr_byte_en = s_apb_PSTRB;

    assign s_apb_PRDATA = cpuif_rd_data;
    assign s_apb_PREADY = cpuif_rd_ack;
    assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;

    //--------------------------------------------------------------------------
    // Fanout CPU Bus interface signals
    //--------------------------------------------------------------------------
    assign m_apb_pcie_top_regs_PSEL = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
    assign m_apb_pcie_top_regs_PENABLE = s_apb_PENABLE;
    assign m_apb_pcie_top_regs_PWRITE = cpuif_wr_sel.pcie_top_regs;
    assign m_apb_pcie_top_regs_PADDR = s_apb_PADDR[5:0];
    assign m_apb_pcie_top_regs_PPROT = s_apb_PPROT;
    assign m_apb_pcie_top_regs_PWDATA = cpuif_wr_data;
    assign m_apb_pcie_top_regs_PSTRB = cpuif_wr_byte_en;
    assign m_apb_eth_dma_wrapper_regs_PSEL = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
    assign m_apb_eth_dma_wrapper_regs_PENABLE = s_apb_PENABLE;
    assign m_apb_eth_dma_wrapper_regs_PWRITE = cpuif_wr_sel.eth_dma_wrapper_regs;
    assign m_apb_eth_dma_wrapper_regs_PADDR = s_apb_PADDR[7:0];
    assign m_apb_eth_dma_wrapper_regs_PPROT = s_apb_PPROT;
    assign m_apb_eth_dma_wrapper_regs_PWDATA = cpuif_wr_data;
    assign m_apb_eth_dma_wrapper_regs_PSTRB = cpuif_wr_byte_en;

    //--------------------------------------------------------------------------
    // Fanin CPU Bus interface signals
    //--------------------------------------------------------------------------
    always_comb begin
        cpuif_rd_ack = '0;
        cpuif_rd_err = '0;
        cpuif_rd_data = '0;
        if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
            cpuif_rd_ack = m_apb_pcie_top_regs_PREADY;
            cpuif_rd_err = m_apb_pcie_top_regs_PSLVERR;
        end
        if (cpuif_rd_sel.pcie_top_regs) begin
            cpuif_rd_data = m_apb_pcie_top_regs_PRDATA;
        end
        if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
            cpuif_rd_ack = m_apb_eth_dma_wrapper_regs_PREADY;
            cpuif_rd_err = m_apb_eth_dma_wrapper_regs_PSLVERR;
        end
        if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
            cpuif_rd_data = m_apb_eth_dma_wrapper_regs_PRDATA;
        end
    end

    //--------------------------------------------------------------------------
    // Write Address Decoder
    //--------------------------------------------------------------------------
    always_comb begin
        // Default all write select signals to 0
        cpuif_wr_sel = '{default: '0};

        if (cpuif_req && cpuif_wr_en) begin
            // A write request is pending
            if ((cpuif_wr_addr < (9'h38))) begin
                cpuif_wr_sel.pcie_top_regs = 1'b1;
            end
            else if ((cpuif_wr_addr >= (9'h100)) && (cpuif_wr_addr < (9'h1b8))) begin
                cpuif_wr_sel.eth_dma_wrapper_regs = 1'b1;
            end
            else begin
                cpuif_wr_sel.cpuif_err = 1'b1;
            end
        end else begin
            // No write request, all select signals remain 0
        end
    end

    //--------------------------------------------------------------------------
    // Read Address Decoder
    //--------------------------------------------------------------------------
    always_comb begin
        // Default all read select signals to 0
        cpuif_rd_sel = '{default: '0};

        if (cpuif_req && cpuif_rd_en) begin
            // A read request is pending
            if ((cpuif_rd_addr < (9'h38))) begin
                cpuif_rd_sel.pcie_top_regs = 1'b1;
            end
            else if ((cpuif_rd_addr >= (9'h100)) && (cpuif_rd_addr < (9'h1b8))) begin
                cpuif_rd_sel.eth_dma_wrapper_regs = 1'b1;
            end
            else begin
                cpuif_rd_sel.cpuif_err = 1'b1;
            end
        end else begin
            // No read request, all select signals remain 0
        end
    end
endmodule