166 lines
8.4 KiB
Python
166 lines
8.4 KiB
Python
class AddrNode():
|
|
addr: int
|
|
class alibaba_pcie_top_regsClass(AddrNode):
|
|
class pcie_top_regsClass(AddrNode):
|
|
class pcie_dma_regsClass(AddrNode):
|
|
class dma_rdClass(AddrNode):
|
|
class src_addr_lowClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class src_addr_highClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class dst_addrClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class lengthClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class triggerClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class doneClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
|
|
self.src_addr_high = self.src_addr_highClass(self.addr + 4)
|
|
self.dst_addr = self.dst_addrClass(self.addr + 8)
|
|
self.length = self.lengthClass(self.addr + 12)
|
|
self.trigger = self.triggerClass(self.addr + 16)
|
|
self.done = self.doneClass(self.addr + 20)
|
|
class dma_wrClass(AddrNode):
|
|
class dst_addr_lowClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class dst_addr_highClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class src_addrClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class lengthClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class triggerClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class doneClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
|
|
self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
|
|
self.src_addr = self.src_addrClass(self.addr + 8)
|
|
self.length = self.lengthClass(self.addr + 12)
|
|
self.trigger = self.triggerClass(self.addr + 16)
|
|
self.done = self.doneClass(self.addr + 20)
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.dma_rd = self.dma_rdClass(self.addr + 0)
|
|
self.dma_wr = self.dma_wrClass(self.addr + 32)
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 0)
|
|
class eth_dma_wrapper_regsClass(AddrNode):
|
|
class eth_mac_25g_us_regsClass(AddrNode):
|
|
class commonClass(AddrNode):
|
|
class xcvr_gtpowergood_outClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class xcvr_qpll0lock_outClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class xcvr_qpll1lock_outClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.xcvr_gtpowergood_out = self.xcvr_gtpowergood_outClass(self.addr + 0)
|
|
self.xcvr_qpll0lock_out = self.xcvr_qpll0lock_outClass(self.addr + 4)
|
|
self.xcvr_qpll1lock_out = self.xcvr_qpll1lock_outClass(self.addr + 8)
|
|
class lanesClass(AddrNode):
|
|
class rx_block_lockClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class rx_statusClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.rx_block_lock = self.rx_block_lockClass(self.addr + 0)
|
|
self.rx_status = self.rx_statusClass(self.addr + 4)
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.common = self.commonClass(self.addr + 0)
|
|
self.lanes = [self.lanesClass(self.addr + 32 + 8*i) for i in range(2)]
|
|
class pcie_dma_regsClass(AddrNode):
|
|
class dma_rdClass(AddrNode):
|
|
class src_addr_lowClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class src_addr_highClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class dst_addrClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class lengthClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class triggerClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class doneClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
|
|
self.src_addr_high = self.src_addr_highClass(self.addr + 4)
|
|
self.dst_addr = self.dst_addrClass(self.addr + 8)
|
|
self.length = self.lengthClass(self.addr + 12)
|
|
self.trigger = self.triggerClass(self.addr + 16)
|
|
self.done = self.doneClass(self.addr + 20)
|
|
class dma_wrClass(AddrNode):
|
|
class dst_addr_lowClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class dst_addr_highClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class src_addrClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class lengthClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class triggerClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
class doneClass(AddrNode):
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
|
|
self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
|
|
self.src_addr = self.src_addrClass(self.addr + 8)
|
|
self.length = self.lengthClass(self.addr + 12)
|
|
self.trigger = self.triggerClass(self.addr + 16)
|
|
self.done = self.doneClass(self.addr + 20)
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.dma_rd = self.dma_rdClass(self.addr + 0)
|
|
self.dma_wr = self.dma_wrClass(self.addr + 32)
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.eth_mac_25g_us_regs = self.eth_mac_25g_us_regsClass(self.addr + 0)
|
|
self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 128)
|
|
def __init__(self, addr: int = 0):
|
|
self.addr = addr
|
|
self.pcie_top_regs = self.pcie_top_regsClass(self.addr + 0)
|
|
self.eth_dma_wrapper_regs = self.eth_dma_wrapper_regsClass(self.addr + 256)
|