191 lines
7.1 KiB
C
191 lines
7.1 KiB
C
// Generated by PeakRDL-cheader - A free and open-source header generator
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// https://github.com/SystemRDL/PeakRDL-cheader
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#ifndef ALIBABA_PCIE_TOP_REGS_H
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#define ALIBABA_PCIE_TOP_REGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <assert.h>
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// Reg - pcie_dma_regs::dma_rd::src_addr_low
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bm 0xffffffff
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bp 0
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bw 32
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_reset 0x0
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// Reg - pcie_dma_regs::dma_rd::src_addr_high
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bm 0xffffffff
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bp 0
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bw 32
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#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_reset 0x0
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// Reg - pcie_dma_regs::dma_rd::dst_addr
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#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bm 0xffff
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#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bp 0
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#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bw 16
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#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_reset 0x0
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// Reg - pcie_dma_regs::dma_rd::length
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#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bm 0xffff
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#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bp 0
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#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bw 16
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#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_reset 0x0
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// Reg - pcie_dma_regs::dma_rd::trigger
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#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bm 0x1
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#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bp 0
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#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bw 1
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#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_reset 0x0
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// Reg - pcie_dma_regs::dma_rd::done
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#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bm 0x1
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#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bp 0
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#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bw 1
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#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_reset 0x0
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// Regfile - pcie_dma_regs::dma_rd
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typedef struct __attribute__ ((__packed__)) {
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uint32_t src_addr_low;
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uint32_t src_addr_high;
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uint32_t dst_addr;
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uint32_t length;
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uint32_t trigger;
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uint32_t done;
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} pcie_dma_regs__dma_rd_t;
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// Reg - pcie_dma_regs::dma_wr::dst_addr_low
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bm 0xffffffff
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bp 0
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bw 32
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_reset 0x0
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// Reg - pcie_dma_regs::dma_wr::dst_addr_high
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bm 0xffffffff
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bp 0
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bw 32
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#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_reset 0x0
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// Reg - pcie_dma_regs::dma_wr::src_addr
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#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bm 0xffff
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#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bp 0
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#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bw 16
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#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_reset 0x0
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// Reg - pcie_dma_regs::dma_wr::length
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#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bm 0xffff
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#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bp 0
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#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bw 16
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#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_reset 0x0
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// Reg - pcie_dma_regs::dma_wr::trigger
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#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bm 0x1
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#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bp 0
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#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bw 1
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#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_reset 0x0
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// Reg - pcie_dma_regs::dma_wr::done
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#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bm 0x1
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#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bp 0
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#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bw 1
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#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_reset 0x0
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// Regfile - pcie_dma_regs::dma_wr
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typedef struct __attribute__ ((__packed__)) {
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uint32_t dst_addr_low;
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uint32_t dst_addr_high;
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uint32_t src_addr;
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uint32_t length;
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uint32_t trigger;
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uint32_t done;
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} pcie_dma_regs__dma_wr_t;
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// Addrmap - pcie_dma_regs
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typedef struct __attribute__ ((__packed__)) {
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pcie_dma_regs__dma_rd_t dma_rd;
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uint8_t RESERVED_18_1f[0x8];
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pcie_dma_regs__dma_wr_t dma_wr;
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} pcie_dma_regs_t;
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// Addrmap - pcie_top_regs
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typedef struct __attribute__ ((__packed__)) {
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pcie_dma_regs_t pcie_dma_regs;
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} pcie_top_regs_t;
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// Reg - eth_mac_25g_us_regs::common::xcvr_gtpowergood_out
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bm 0x1
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bp 0
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bw 1
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_reset 0x0
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// Reg - eth_mac_25g_us_regs::common::xcvr_qpll0lock_out
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bm 0x1
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bp 0
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bw 1
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_reset 0x0
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// Reg - eth_mac_25g_us_regs::common::xcvr_qpll1lock_out
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bm 0x1
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bp 0
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bw 1
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#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_reset 0x0
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// Regfile - eth_mac_25g_us_regs::common
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typedef struct __attribute__ ((__packed__)) {
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uint32_t xcvr_gtpowergood_out;
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uint32_t xcvr_qpll0lock_out;
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uint32_t xcvr_qpll1lock_out;
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} eth_mac_25g_us_regs__common_t;
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// Reg - eth_mac_25g_us_regs::lane::rx_block_lock
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#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bm 0x1
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#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bp 0
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#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bw 1
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#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_reset 0x0
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// Reg - eth_mac_25g_us_regs::lane::rx_status
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#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bm 0x1
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#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bp 0
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#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bw 1
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#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_reset 0x0
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// Regfile - eth_mac_25g_us_regs::lane
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typedef struct __attribute__ ((__packed__)) {
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uint32_t rx_block_lock;
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uint32_t rx_status;
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uint8_t RESERVED_8_1f[0x18];
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} eth_mac_25g_us_regs__lane__stride20_t;
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// Addrmap - eth_mac_25g_us_regs
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typedef struct __attribute__ ((__packed__)) {
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eth_mac_25g_us_regs__common_t common;
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uint8_t RESERVED_c_1f[0x14];
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eth_mac_25g_us_regs__lane__stride20_t lanes[2];
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} eth_mac_25g_us_regs_t;
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// Addrmap - eth_dma_wrapper_regs
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typedef struct __attribute__ ((__packed__)) {
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eth_mac_25g_us_regs_t eth_mac_25g_us_regs;
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uint8_t RESERVED_60_7f[0x20];
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pcie_dma_regs_t pcie_dma_regs;
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} eth_dma_wrapper_regs_t;
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// Addrmap - alibaba_pcie_top_regs
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typedef struct __attribute__ ((__packed__)) {
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pcie_top_regs_t pcie_top_regs;
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uint8_t RESERVED_38_ff[0xc8];
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eth_dma_wrapper_regs_t eth_dma_wrapper_regs;
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} alibaba_pcie_top_regs_t;
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static_assert(sizeof(alibaba_pcie_top_regs_t) == 0x1b8, "Packing error");
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#ifdef __cplusplus
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}
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#endif
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#endif /* ALIBABA_PCIE_TOP_REGS_H */
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