121 lines
3.1 KiB
Systemverilog
121 lines
3.1 KiB
Systemverilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11/05/2025 10:00:52 PM
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// Design Name:
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// Module Name: alibaba_pcie_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module alibaba_pcie(
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input wire [7:0] pci_exp_rxp,
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input wire [7:0] pci_exp_rxn,
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output wire [7:0] pci_exp_txp,
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output wire [7:0] pci_exp_txn,
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input wire pcie_mgt_refclk_p,
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input wire pcie_mgt_refclk_n,
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input wire pcie_reset_n,
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input wire sfp_mgt_clk_p,
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input wire sfp_mgt_clk_n,
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output wire sfp_txp [2],
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output wire sfp_txn [2],
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input wire sfp_rxp [2],
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input wire sfp_rxn [2],
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output wire [3:0] Led_o
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);
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logic clk_250;
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logic rst_250;
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taxi_axil_if m_axil_rd();
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taxi_axil_if m_axil_wr();
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taxi_apb_if #(.ADDR_W(alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)) s_apb();
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taxi_apb_if #(.ADDR_W(pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)) pcie_apb();
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taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_apb();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
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taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
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alibaba_pcie_top_regs u_alibaba_pcie_top_regs (
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.s_apb (s_apb),
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.m_apb_pcie_top_regs (pcie_apb),
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.m_apb_eth_dma_wrapper_regs (eth_apb)
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);
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taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
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.clk (clk_250),
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.rst (rst_250),
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.s_axil_wr (m_axil_wr),
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.s_axil_rd (m_axil_rd),
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.m_apb (s_apb)
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);
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eth_dma_wrapper u_eth_dma_wrapper (
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.clk_250 (clk_250),
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.rst_250 (rst_250),
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.sfp_mgt_clk_p (sfp_mgt_clk_p),
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.sfp_mgt_clk_n (sfp_mgt_clk_n),
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.sfp_txp (sfp_txp),
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.sfp_txn (sfp_txn),
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.sfp_rxp (sfp_rxp),
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.sfp_rxn (sfp_rxn),
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.wr_dma_mst (dma_ram_eth_wr_if),
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.rd_dma_mst (dma_ram_eth_rd_if),
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.s_apb (eth_apb)
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);
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pcie_top u_pcie_top(
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.pci_exp_rxp (pci_exp_rxp),
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.pci_exp_rxn (pci_exp_rxn),
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.pci_exp_txp (pci_exp_txp),
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.pci_exp_txn (pci_exp_txn),
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.pcie_mgt_refclk_p (pcie_mgt_refclk_p),
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.pcie_mgt_refclk_n (pcie_mgt_refclk_n),
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.pcie_reset_n (pcie_reset_n),
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.user_lnk_up (Led_o[0]),
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.phy_rdy_out (Led_o[1]),
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.o_clk_250 (clk_250),
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.o_rst_250 (rst_250),
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.dma_ram_eth_wr_if (dma_ram_eth_wr_if),
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.dma_ram_eth_rd_if (dma_ram_eth_rd_if),
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.m_axil_rd (m_axil_rd),
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.m_axil_wr (m_axil_wr),
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.s_apb (pcie_apb)
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);
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endmodule
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