diff --git a/ip/pcie_7x_0/pcie_7x_0.xci b/ip/pcie_7x_0/pcie_7x_0.xci index d00e6a7..2335d5f 100644 --- a/ip/pcie_7x_0/pcie_7x_0.xci +++ b/ip/pcie_7x_0/pcie_7x_0.xci @@ -61,11 +61,11 @@ "Revision_ID": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], "Subsystem_Vendor_ID": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ], "Subsystem_ID": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ], - "Class_Code_Base": [ { "value": "FF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "Class_Code_Sub": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Class_Code_Base": [ { "value": "05", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Class_Code_Sub": [ { "value": "80", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Class_Code_Interface": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], - "Base_Class_Menu": [ { "value": "Device_does_not_fit_in_any_defined_classes", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "Sub_Class_Interface_Menu": [ { "value": "Unknown", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Base_Class_Menu": [ { "value": "Memory_controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Sub_Class_Interface_Menu": [ { "value": "Other_memory_controller", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Cardbus_CIS_Pointer": [ { "value": "00000000", "resolve_type": "user", "usage": "all" } ], "PCIe_Cap_Slot_Implemented": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Max_Payload_Size": [ { "value": "512_bytes", "value_src": "user", "resolve_type": "user", "usage": "all" } ], @@ -173,7 +173,7 @@ "UR_PRS_RESPONSE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Silicon_Rev": [ { "value": "GES_and_Production", "resolve_type": "user", "usage": "all" } ], "Pcie_fast_config": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], - "PCIe_Debug_Ports": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PCIe_Debug_Ports": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "Ref_Clk_Freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Cost_Table": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "UR_Atomic": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -274,7 +274,7 @@ "rev_id": [ { "value": "00", "resolve_type": "generated", "usage": "all" } ], "subsys_ven_id": [ { "value": "10EE", "resolve_type": "generated", "usage": "all" } ], "subsys_id": [ { "value": "0007", "resolve_type": "generated", "usage": "all" } ], - "class_code": [ { "value": "FF0100", "resolve_type": "generated", "usage": "all" } ], + "class_code": [ { "value": "058000", "resolve_type": "generated", "usage": "all" } ], "cardbus_cis_ptr": [ { "value": "00000000", "resolve_type": "generated", "usage": "all" } ], "cap_ver": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ], "c_pcie_cap_slot_implemented": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], @@ -394,7 +394,7 @@ "c_upconfig_capable": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ], "c_disable_scrambling": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "c_disable_tx_aspm_l0s": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "c_pcie_dbg_ports": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ], + "c_pcie_dbg_ports": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "pci_exp_ref_freq": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], "c_xlnx_ref_board": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ], "c_pcie_blk_locn": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], @@ -523,14 +523,7 @@ "cfg_interrupt_stat": [ { "direction": "in", "driver_value": "0" } ], "cfg_pciecap_interrupt_msgnum": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ], "sys_clk": [ { "direction": "in" } ], - "sys_rst_n": [ { "direction": "in" } ], - "pcie_drp_clk": [ { "direction": "in", "driver_value": "1" } ], - "pcie_drp_en": [ { "direction": "in", "driver_value": "0" } ], - "pcie_drp_we": [ { "direction": "in", "driver_value": "0" } ], - "pcie_drp_addr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ], - "pcie_drp_di": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], - "pcie_drp_do": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], - "pcie_drp_rdy": [ { "direction": "out" } ] + "sys_rst_n": [ { "direction": "in" } ] }, "interfaces": { "m_axis_rx": { @@ -600,19 +593,6 @@ "txp": [ { "physical_name": "pci_exp_txp" } ] } }, - "drp": { - "vlnv": "xilinx.com:interface:drp:1.0", - "abstraction_type": "xilinx.com:interface:drp_rtl:1.0", - "mode": "slave", - "port_maps": { - "DADDR": [ { "physical_name": "pcie_drp_addr" } ], - "DEN": [ { "physical_name": "pcie_drp_en" } ], - "DI": [ { "physical_name": "pcie_drp_di" } ], - "DO": [ { "physical_name": "pcie_drp_do" } ], - "DRDY": [ { "physical_name": "pcie_drp_rdy" } ], - "DWE": [ { "physical_name": "pcie_drp_we" } ] - } - }, "CLK.sys_clk": { "vlnv": "xilinx.com:signal:clock:1.0", "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", diff --git a/src/artix_pcie.sv b/src/artix_pcie.sv index 30f73fa..f1411c0 100644 --- a/src/artix_pcie.sv +++ b/src/artix_pcie.sv @@ -85,15 +85,7 @@ pcie_7x_0 u_pcie_7x_0 ( .cfg_pciecap_interrupt_msgnum('0), .sys_clk (pcie_refclk), - .sys_rst_n (rst_n), - - .pcie_drp_clk ('0), - .pcie_drp_en ('0), - .pcie_drp_we ('0), - .pcie_drp_addr ('0), - .pcie_drp_di ('0), - .pcie_drp_do (), - .pcie_drp_rdy () + .sys_rst_n (rst_n) ); assign axis_tready = '1;