bslathi19/artix_pcie
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This commit is contained in:
Byron Lathi
2025-01-26 15:13:57 -08:00
parent 952e141e03
commit 36cba07242
4 changed files with 749 additions and 1 deletions
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84
src/artix_pcie.sv
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@@ -1,5 +1,87 @@
module artix_test(
input wire sys_clk_p,
input wire sys_clk_n,
input wire rst_n,
output wire [1 : 0] pci_exp_txp,
output wire [1 : 0] pci_exp_txn,
input wire [1 : 0] pci_exp_rxp,
input wire [1 : 0] pci_exp_rxn
);
logic clk_200;
logic axi_aclk;
logic axi_aresetn;
logic [63 : 0] s_axis_c2h_tdata_0;
logic s_axis_c2h_tlast_0;
logic s_axis_c2h_tvalid_0;
logic s_axis_c2h_tready_0;
logic [7 : 0] s_axis_c2h_tkeep_0;
logic [63 : 0] m_axis_h2c_tdata_0;
logic m_axis_h2c_tlast_0;
logic m_axis_h2c_tvalid_0;
logic m_axis_h2c_tready_0;
logic [7 : 0] m_axis_h2c_tkeep_0;
clk_wiz_0 u_clk_wiz0
(
// Clock out ports
.clk_out1(clk_200), // output clk_out1
// Clock in ports
.clk_in1_p(sys_clk_p), // input clk_in1_p
.clk_in1_n(sys_clk_n) // input clk_in1_n
);
xdma_0 u_xdma (
.sys_clk(clk_200),
.sys_rst_n(rst_n),
.user_lnk_up(),
.pci_exp_txp(pci_exp_txp),
.pci_exp_txn(pci_exp_txn),
.pci_exp_rxp(pci_exp_rxp),
.pci_exp_rxn(pci_exp_rxn),
.axi_aclk(axi_aclk),
.axi_aresetn(axi_aresetn),
.usr_irq_req('0),
.usr_irq_ack(),
.msi_enable(),
.msi_vector_width(),
.cfg_mgmt_addr('0),
.cfg_mgmt_write('0),
.cfg_mgmt_write_data('0),
.cfg_mgmt_byte_enable('0),
.cfg_mgmt_read('0),
.cfg_mgmt_read_data(),
.cfg_mgmt_read_write_done(),
.cfg_mgmt_type1_cfg_reg_access('0),
.s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),
.s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),
.s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),
.s_axis_c2h_tready_0(s_axis_c2h_tready_0),
.s_axis_c2h_tkeep_0(s_axis_c2h_tkeep_0),
.m_axis_h2c_tdata_0(m_axis_h2c_tdata_0),
.m_axis_h2c_tlast_0(m_axis_h2c_tlast_0),
.m_axis_h2c_tvalid_0(m_axis_h2c_tvalid_0),
.m_axis_h2c_tready_0(m_axis_h2c_tready_0),
.m_axis_h2c_tkeep_0(m_axis_h2c_tkeep_0)
);
axis_data_fifo_0 u_axis_data_fifo (
.s_axis_aresetn(axi_aresetn),
.s_axis_aclk(axi_aclk),
.s_axis_tvalid(m_axis_h2c_tvalid_0),
.s_axis_tready(m_axis_h2c_tready_0),
.s_axis_tdata(m_axis_h2c_tdata_0),
.s_axis_tkeep(m_axis_h2c_tkeep_0),
.s_axis_tlast(m_axis_h2c_tlast_0),
.m_axis_tvalid(s_axis_c2h_tvalid_0),
.m_axis_tready(s_axis_c2h_tready_0),
.m_axis_tdata(s_axis_c2h_tdata_0),
.m_axis_tkeep(s_axis_c2h_tkeep_0),
.m_axis_tlast(s_axis_c2h_tlast_0)
);
endmodule

10
src/top.xdc
View File

@@ -59,6 +59,16 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN K13 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
# PCIE
set_property PACKAGE_PIN D9 [get_ports {pci_exp_rxp[0]}]
set_property PACKAGE_PIN B10 [get_ports {pci_exp_rxp[1]}]
set_property PACKAGE_PIN C9 [get_ports {pci_exp_rxn[0]}]
set_property PACKAGE_PIN A10 [get_ports {pci_exp_rxn[1]}]
set_property PACKAGE_PIN D7 [get_ports {pci_exp_txp[0]}]
set_property PACKAGE_PIN B6 [get_ports {pci_exp_txp[1]}]
set_property PACKAGE_PIN C7 [get_ports {pci_exp_txn[0]}]
set_property PACKAGE_PIN A6 [get_ports {pci_exp_txn[1]}]
set_false_path -reset_path -from [get_clocks -of_objects [get_pins u_clk_wiz0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks rgmii_rxc]