bslathi19/artix_pcie
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Add ILA, switch to 1 lane

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This commit is contained in:
Byron Lathi
2025-01-26 17:26:12 -08:00
parent c391889a03
commit b2fe92b9c9
4 changed files with 6406 additions and 67 deletions
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62
src/artix_pcie.sv
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@@ -4,13 +4,15 @@ module artix_pcie(
input wire rst_n,
input wire pcie_exp_clkp
input wire pcie_exp_clkn
input wire pcie_exp_clkp,
input wire pcie_exp_clkn,
output wire [1 : 0] pci_exp_txp,
output wire [1 : 0] pci_exp_txn,
input wire [1 : 0] pci_exp_rxp,
input wire [1 : 0] pci_exp_rxn
output wire [0 : 0] pci_exp_txp,
output wire [0 : 0] pci_exp_txn,
input wire [0 : 0] pci_exp_rxp,
input wire [0 : 0] pci_exp_rxn,
output wire [3:0] led
);
logic pcie_refclk;
@@ -45,25 +47,17 @@ IBUFDS_GTE2 #(
xdma_0 u_xdma (
.sys_clk(pcie_refclk),
.sys_rst_n(rst_n), // this reset is not synchronized. Should it be?
.user_lnk_up(),
.pci_exp_txp(pci_exp_txp),
.pci_exp_txn(pci_exp_txn),
.pci_exp_rxp(pci_exp_rxp),
.pci_exp_rxn(pci_exp_rxn),
.user_lnk_up(led[0]),
.pci_exp_txp(pci_exp_txp[0]),
.pci_exp_txn(pci_exp_txn[0]),
.pci_exp_rxp(pci_exp_rxp[0]),
.pci_exp_rxn(pci_exp_rxn[0]),
.axi_aclk(axi_aclk),
.axi_aresetn(axi_aresetn),
.usr_irq_req('0),
.usr_irq_ack(),
.msi_enable(),
.msi_vector_width(),
.cfg_mgmt_addr('0),
.cfg_mgmt_write('0),
.cfg_mgmt_write_data('0),
.cfg_mgmt_byte_enable('0),
.cfg_mgmt_read('0),
.cfg_mgmt_read_data(),
.cfg_mgmt_read_write_done(),
.cfg_mgmt_type1_cfg_reg_access('0),
.s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),
.s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),
.s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),
@@ -91,4 +85,34 @@ axis_data_fifo_0 u_axis_data_fifo (
.m_axis_tlast(s_axis_c2h_tlast_0)
);
ila_0 u_ula_c2h (
.clk(axi_aclk), // input wire clk
.probe0(s_axis_c2h_tready_0), // input wire [0:0] probe0
.probe1(s_axis_c2h_tdata_0), // input wire [63:0] probe1
.probe2('0), // input wire [7:0] probe2
.probe3(s_axis_c2h_tvalid_0), // input wire [0:0] probe3
.probe4(s_axis_c2h_tlast_0), // input wire [0:0] probe4
.probe5('0), // input wire [0:0] probe5
.probe6(s_axis_c2h_tdata_0), // input wire [7:0] probe6
.probe7('0), // input wire [0:0] probe7
.probe8('0) // input wire [0:0] probe8
);
ila_0 u_ula_c2h (
.clk(axi_aclk), // input wire clk
.probe0(m_axis_h2c_tready_0), // input wire [0:0] probe0
.probe1(m_axis_h2c_tdata_0), // input wire [63:0] probe1
.probe2('0), // input wire [7:0] probe2
.probe3(m_axis_h2c_tvalid_0), // input wire [0:0] probe3
.probe4(m_axis_h2c_tlast_0), // input wire [0:0] probe4
.probe5('0), // input wire [0:0] probe5
.probe6(m_axis_h2c_tdata_0), // input wire [7:0] probe6
.probe7('0), // input wire [0:0] probe7
.probe8('0) // input wire [0:0] probe8
);
endmodule