Add ILA, switch to 1 lane
This commit is contained in:
6338
ip/ila_0/ila_0.xci
Normal file
6338
ip/ila_0/ila_0.xci
Normal file
File diff suppressed because it is too large
Load Diff
@@ -12,7 +12,7 @@
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"mode_selection": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
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"mode_selection": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
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"device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
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"pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
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"pl_link_cap_max_link_width": [ { "value": "X2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"pl_link_cap_max_link_width": [ { "value": "X1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"pl_link_cap_max_link_speed": [ { "value": "2.5_GT/s", "resolve_type": "user", "usage": "all" } ],
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"pl_link_cap_max_link_speed": [ { "value": "2.5_GT/s", "resolve_type": "user", "usage": "all" } ],
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"ref_clk_freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"ref_clk_freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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@@ -32,7 +32,7 @@
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"ext_startup_primitive": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"ext_startup_primitive": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"enable_code": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"enable_code": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
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"vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
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"pf0_device_id": [ { "value": "7012", "resolve_type": "user", "usage": "all" } ],
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"pf0_device_id": [ { "value": "7011", "resolve_type": "user", "usage": "all" } ],
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"pf0_revision_id": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"pf0_revision_id": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"pf0_subsystem_vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
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"pf0_subsystem_vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
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"pf0_subsystem_id": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ],
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"pf0_subsystem_id": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ],
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@@ -91,13 +91,13 @@
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"coreclk_freq": [ { "value": "500", "resolve_type": "user", "usage": "all" } ],
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"coreclk_freq": [ { "value": "500", "resolve_type": "user", "usage": "all" } ],
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"plltype": [ { "value": "CPLL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"plltype": [ { "value": "CPLL", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"xdma_axi_intf_mm": [ { "value": "AXI_Stream", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"xdma_axi_intf_mm": [ { "value": "AXI_Stream", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"xdma_pcie_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"xdma_pcie_64bit_en": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"silicon_rev": [ { "value": "Pre-Production", "resolve_type": "user", "usage": "all" } ],
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"silicon_rev": [ { "value": "Pre-Production", "resolve_type": "user", "usage": "all" } ],
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"xdma_dsc_bypass": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"xdma_dsc_bypass": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"performance": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"performance": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"pcie_extended_tag": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"pcie_extended_tag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"rx_detect": [ { "value": "Default", "resolve_type": "user", "usage": "all" } ],
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"rx_detect": [ { "value": "Default", "resolve_type": "user", "usage": "all" } ],
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"pf0_link_status_slot_clock_config": [ { "value": "true", "resolve_type": "user", "usage": "all" } ],
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"pf0_link_status_slot_clock_config": [ { "value": "true", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"dsc_bypass_rd": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"dsc_bypass_rd": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"dsc_bypass_wr": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"dsc_bypass_wr": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"xdma_sts_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"xdma_sts_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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@@ -113,7 +113,7 @@
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"pf1_msix_cap_table_bir": [ { "value": "BAR_0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf1_msix_cap_table_bir": [ { "value": "BAR_0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf1_msix_cap_pba_offset": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf1_msix_cap_pba_offset": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf1_msix_cap_pba_bir": [ { "value": "BAR_0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf1_msix_cap_pba_bir": [ { "value": "BAR_0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"cfg_mgmt_if": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"cfg_mgmt_if": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ins_loss_profile": [ { "value": "Add-in_Card", "resolve_type": "user", "usage": "all" } ],
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"ins_loss_profile": [ { "value": "Add-in_Card", "resolve_type": "user", "usage": "all" } ],
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"axil_master_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"axil_master_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"axi_bypass_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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"axi_bypass_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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@@ -718,15 +718,15 @@
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"pf3_sriov_bar5_prefetchable": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf3_sriov_bar5_prefetchable": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf3_sriov_bar5_size": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"pf3_sriov_bar5_size": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"pf3_sriov_bar5_scale": [ { "value": "Kilobytes", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf3_sriov_bar5_scale": [ { "value": "Kilobytes", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pcie_id_if": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"pcie_id_if": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"pf0_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
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"pf0_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ],
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"pf1_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf1_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf2_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf2_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf3_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf3_vendor_id_mqdma": [ { "value": "10EE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF0_DEVICE_ID_mqdma": [ { "value": "9012", "resolve_type": "user", "usage": "all" } ],
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"PF0_DEVICE_ID_mqdma": [ { "value": "9011", "resolve_type": "user", "usage": "all" } ],
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"PF1_DEVICE_ID_mqdma": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ],
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"PF1_DEVICE_ID_mqdma": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ],
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"PF2_DEVICE_ID_mqdma": [ { "value": "9212", "resolve_type": "user", "usage": "all" } ],
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"PF2_DEVICE_ID_mqdma": [ { "value": "9211", "resolve_type": "user", "usage": "all" } ],
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"PF3_DEVICE_ID_mqdma": [ { "value": "9312", "resolve_type": "user", "usage": "all" } ],
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"PF3_DEVICE_ID_mqdma": [ { "value": "9311", "resolve_type": "user", "usage": "all" } ],
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"PF0_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"PF0_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"PF1_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"PF1_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"PF2_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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"PF2_REVISION_ID_mqdma": [ { "value": "00", "resolve_type": "user", "usage": "all" } ],
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@@ -772,26 +772,26 @@
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"PF0_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF0_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF0_SRIOV_FUNC_DEP_LINK": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_FUNC_DEP_LINK": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_VF_DEVICE_ID": [ { "value": "A032", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_VF_DEVICE_ID": [ { "value": "A031", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF0_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF1_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF1_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF1_SRIOV_FUNC_DEP_LINK": [ { "value": "0001", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_FUNC_DEP_LINK": [ { "value": "0001", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF1_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF1_SRIOV_VF_DEVICE_ID": [ { "value": "A132", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF1_SRIOV_VF_DEVICE_ID": [ { "value": "A131", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF2_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF2_SRIOV_FUNC_DEP_LINK": [ { "value": "0002", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_FUNC_DEP_LINK": [ { "value": "0002", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF2_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF2_SRIOV_VF_DEVICE_ID": [ { "value": "A232", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF2_SRIOV_VF_DEVICE_ID": [ { "value": "A231", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_CAP_INITIAL_VF": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_CAP_VER": [ { "value": "1", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF3_SRIOV_FIRST_VF_OFFSET": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
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"PF3_SRIOV_FUNC_DEP_LINK": [ { "value": "0003", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_FUNC_DEP_LINK": [ { "value": "0003", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF3_SRIOV_SUPPORTED_PAGE_SIZE": [ { "value": "00000553", "resolve_type": "user", "usage": "all" } ],
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"PF3_SRIOV_VF_DEVICE_ID": [ { "value": "A332", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"PF3_SRIOV_VF_DEVICE_ID": [ { "value": "A331", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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"pf0_ari_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf0_ari_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf0_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf0_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf1_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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"pf1_msix_enabled_mqdma": [ { "value": "false", "resolve_type": "user", "usage": "all" } ],
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@@ -965,7 +965,7 @@
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"PL_UPSTREAM_FACING": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ],
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"PL_UPSTREAM_FACING": [ { "value": "true", "resolve_type": "generated", "usage": "all" } ],
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"TL_LEGACY_MODE_ENABLE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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"TL_LEGACY_MODE_ENABLE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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"PCIE_BLK_LOCN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"PCIE_BLK_LOCN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"PL_LINK_CAP_MAX_LINK_SPEED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"PL_LINK_CAP_MAX_LINK_SPEED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"REF_CLK_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"REF_CLK_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"DRP_CLK_SEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"DRP_CLK_SEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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@@ -985,7 +985,7 @@
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"MCAP_ENABLEMENT": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
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"MCAP_ENABLEMENT": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
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"EXT_STARTUP_PRIMITIVE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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"EXT_STARTUP_PRIMITIVE": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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||||||
"PF0_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
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"PF0_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
"PF0_DEVICE_ID": [ { "value": "0x7012", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
"PF0_DEVICE_ID": [ { "value": "0x7011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
"PF0_REVISION_ID": [ { "value": "0x00", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
"PF0_REVISION_ID": [ { "value": "0x00", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
"PF0_SUBSYSTEM_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
"PF0_SUBSYSTEM_VENDOR_ID": [ { "value": "0x10EE", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
"PF0_SUBSYSTEM_ID": [ { "value": "0x0007", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
"PF0_SUBSYSTEM_ID": [ { "value": "0x0007", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||||
@@ -1083,7 +1083,7 @@
|
|||||||
"RD_CH1_ENABLED": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
"RD_CH1_ENABLED": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
"RD_CH2_ENABLED": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
"RD_CH2_ENABLED": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
"RD_CH3_ENABLED": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
"RD_CH3_ENABLED": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
"CFG_MGMT_IF": [ { "value": "TRUE", "resolve_type": "generated", "usage": "all" } ],
|
"CFG_MGMT_IF": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
"RQ_SEQ_NUM_IGNORE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
"RQ_SEQ_NUM_IGNORE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
"CFG_EXT_IF": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
"CFG_EXT_IF": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
"LEGACY_CFG_EXT_IF": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
"LEGACY_CFG_EXT_IF": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
@@ -1307,24 +1307,16 @@
|
|||||||
"sys_clk": [ { "direction": "in" } ],
|
"sys_clk": [ { "direction": "in" } ],
|
||||||
"sys_rst_n": [ { "direction": "in", "driver_value": "1" } ],
|
"sys_rst_n": [ { "direction": "in", "driver_value": "1" } ],
|
||||||
"user_lnk_up": [ { "direction": "out" } ],
|
"user_lnk_up": [ { "direction": "out" } ],
|
||||||
"pci_exp_txp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
"pci_exp_txp": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
"pci_exp_txn": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
"pci_exp_txn": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
"pci_exp_rxp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
"pci_exp_rxp": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
"pci_exp_rxn": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
"pci_exp_rxn": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
"axi_aclk": [ { "direction": "out" } ],
|
"axi_aclk": [ { "direction": "out" } ],
|
||||||
"axi_aresetn": [ { "direction": "out" } ],
|
"axi_aresetn": [ { "direction": "out" } ],
|
||||||
"usr_irq_req": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
"usr_irq_req": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||||
"usr_irq_ack": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
"usr_irq_ack": [ { "direction": "out", "size_left": "0", "size_right": "0" } ],
|
||||||
"msi_enable": [ { "direction": "out" } ],
|
"msi_enable": [ { "direction": "out" } ],
|
||||||
"msi_vector_width": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
"msi_vector_width": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||||
"cfg_mgmt_addr": [ { "direction": "in", "size_left": "18", "size_right": "0", "driver_value": "0" } ],
|
|
||||||
"cfg_mgmt_write": [ { "direction": "in", "driver_value": "0" } ],
|
|
||||||
"cfg_mgmt_write_data": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
|
||||||
"cfg_mgmt_byte_enable": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
|
||||||
"cfg_mgmt_read": [ { "direction": "in", "driver_value": "0" } ],
|
|
||||||
"cfg_mgmt_read_data": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
|
||||||
"cfg_mgmt_read_write_done": [ { "direction": "out" } ],
|
|
||||||
"cfg_mgmt_type1_cfg_reg_access": [ { "direction": "in", "driver_value": "0" } ],
|
|
||||||
"s_axis_c2h_tdata_0": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
"s_axis_c2h_tdata_0": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ],
|
||||||
"s_axis_c2h_tlast_0": [ { "direction": "in", "driver_value": "0" } ],
|
"s_axis_c2h_tlast_0": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
"s_axis_c2h_tvalid_0": [ { "direction": "in", "driver_value": "0" } ],
|
"s_axis_c2h_tvalid_0": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
@@ -1462,21 +1454,6 @@
|
|||||||
"TVALID": [ { "physical_name": "m_axis_h2c_tvalid_0" } ]
|
"TVALID": [ { "physical_name": "m_axis_h2c_tvalid_0" } ]
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
"pcie_cfg_mgmt": {
|
|
||||||
"vlnv": "xilinx.com:interface:pcie_cfg_mgmt:1.0",
|
|
||||||
"abstraction_type": "xilinx.com:interface:pcie_cfg_mgmt_rtl:1.0",
|
|
||||||
"mode": "slave",
|
|
||||||
"port_maps": {
|
|
||||||
"ADDR": [ { "physical_name": "cfg_mgmt_addr" } ],
|
|
||||||
"BYTE_EN": [ { "physical_name": "cfg_mgmt_byte_enable" } ],
|
|
||||||
"READ_DATA": [ { "physical_name": "cfg_mgmt_read_data" } ],
|
|
||||||
"READ_EN": [ { "physical_name": "cfg_mgmt_read" } ],
|
|
||||||
"READ_WRITE_DONE": [ { "physical_name": "cfg_mgmt_read_write_done" } ],
|
|
||||||
"TYPE1_CFG_REG_ACCESS": [ { "physical_name": "cfg_mgmt_type1_cfg_reg_access" } ],
|
|
||||||
"WRITE_DATA": [ { "physical_name": "cfg_mgmt_write_data" } ],
|
|
||||||
"WRITE_EN": [ { "physical_name": "cfg_mgmt_write" } ]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"pcie_mgt": {
|
"pcie_mgt": {
|
||||||
"vlnv": "xilinx.com:interface:pcie_7x_mgt:1.0",
|
"vlnv": "xilinx.com:interface:pcie_7x_mgt:1.0",
|
||||||
"abstraction_type": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
|
"abstraction_type": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0",
|
||||||
|
|||||||
@@ -4,13 +4,15 @@ module artix_pcie(
|
|||||||
|
|
||||||
input wire rst_n,
|
input wire rst_n,
|
||||||
|
|
||||||
input wire pcie_exp_clkp
|
input wire pcie_exp_clkp,
|
||||||
input wire pcie_exp_clkn
|
input wire pcie_exp_clkn,
|
||||||
|
|
||||||
output wire [1 : 0] pci_exp_txp,
|
output wire [0 : 0] pci_exp_txp,
|
||||||
output wire [1 : 0] pci_exp_txn,
|
output wire [0 : 0] pci_exp_txn,
|
||||||
input wire [1 : 0] pci_exp_rxp,
|
input wire [0 : 0] pci_exp_rxp,
|
||||||
input wire [1 : 0] pci_exp_rxn
|
input wire [0 : 0] pci_exp_rxn,
|
||||||
|
|
||||||
|
output wire [3:0] led
|
||||||
);
|
);
|
||||||
|
|
||||||
logic pcie_refclk;
|
logic pcie_refclk;
|
||||||
@@ -45,25 +47,17 @@ IBUFDS_GTE2 #(
|
|||||||
xdma_0 u_xdma (
|
xdma_0 u_xdma (
|
||||||
.sys_clk(pcie_refclk),
|
.sys_clk(pcie_refclk),
|
||||||
.sys_rst_n(rst_n), // this reset is not synchronized. Should it be?
|
.sys_rst_n(rst_n), // this reset is not synchronized. Should it be?
|
||||||
.user_lnk_up(),
|
.user_lnk_up(led[0]),
|
||||||
.pci_exp_txp(pci_exp_txp),
|
.pci_exp_txp(pci_exp_txp[0]),
|
||||||
.pci_exp_txn(pci_exp_txn),
|
.pci_exp_txn(pci_exp_txn[0]),
|
||||||
.pci_exp_rxp(pci_exp_rxp),
|
.pci_exp_rxp(pci_exp_rxp[0]),
|
||||||
.pci_exp_rxn(pci_exp_rxn),
|
.pci_exp_rxn(pci_exp_rxn[0]),
|
||||||
.axi_aclk(axi_aclk),
|
.axi_aclk(axi_aclk),
|
||||||
.axi_aresetn(axi_aresetn),
|
.axi_aresetn(axi_aresetn),
|
||||||
.usr_irq_req('0),
|
.usr_irq_req('0),
|
||||||
.usr_irq_ack(),
|
.usr_irq_ack(),
|
||||||
.msi_enable(),
|
.msi_enable(),
|
||||||
.msi_vector_width(),
|
.msi_vector_width(),
|
||||||
.cfg_mgmt_addr('0),
|
|
||||||
.cfg_mgmt_write('0),
|
|
||||||
.cfg_mgmt_write_data('0),
|
|
||||||
.cfg_mgmt_byte_enable('0),
|
|
||||||
.cfg_mgmt_read('0),
|
|
||||||
.cfg_mgmt_read_data(),
|
|
||||||
.cfg_mgmt_read_write_done(),
|
|
||||||
.cfg_mgmt_type1_cfg_reg_access('0),
|
|
||||||
.s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),
|
.s_axis_c2h_tdata_0(s_axis_c2h_tdata_0),
|
||||||
.s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),
|
.s_axis_c2h_tlast_0(s_axis_c2h_tlast_0),
|
||||||
.s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),
|
.s_axis_c2h_tvalid_0(s_axis_c2h_tvalid_0),
|
||||||
@@ -91,4 +85,34 @@ axis_data_fifo_0 u_axis_data_fifo (
|
|||||||
.m_axis_tlast(s_axis_c2h_tlast_0)
|
.m_axis_tlast(s_axis_c2h_tlast_0)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
ila_0 u_ula_c2h (
|
||||||
|
.clk(axi_aclk), // input wire clk
|
||||||
|
|
||||||
|
|
||||||
|
.probe0(s_axis_c2h_tready_0), // input wire [0:0] probe0
|
||||||
|
.probe1(s_axis_c2h_tdata_0), // input wire [63:0] probe1
|
||||||
|
.probe2('0), // input wire [7:0] probe2
|
||||||
|
.probe3(s_axis_c2h_tvalid_0), // input wire [0:0] probe3
|
||||||
|
.probe4(s_axis_c2h_tlast_0), // input wire [0:0] probe4
|
||||||
|
.probe5('0), // input wire [0:0] probe5
|
||||||
|
.probe6(s_axis_c2h_tdata_0), // input wire [7:0] probe6
|
||||||
|
.probe7('0), // input wire [0:0] probe7
|
||||||
|
.probe8('0) // input wire [0:0] probe8
|
||||||
|
);
|
||||||
|
|
||||||
|
ila_0 u_ula_c2h (
|
||||||
|
.clk(axi_aclk), // input wire clk
|
||||||
|
|
||||||
|
|
||||||
|
.probe0(m_axis_h2c_tready_0), // input wire [0:0] probe0
|
||||||
|
.probe1(m_axis_h2c_tdata_0), // input wire [63:0] probe1
|
||||||
|
.probe2('0), // input wire [7:0] probe2
|
||||||
|
.probe3(m_axis_h2c_tvalid_0), // input wire [0:0] probe3
|
||||||
|
.probe4(m_axis_h2c_tlast_0), // input wire [0:0] probe4
|
||||||
|
.probe5('0), // input wire [0:0] probe5
|
||||||
|
.probe6(m_axis_h2c_tdata_0), // input wire [7:0] probe6
|
||||||
|
.probe7('0), // input wire [0:0] probe7
|
||||||
|
.probe8('0) // input wire [0:0] probe8
|
||||||
|
);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
@@ -62,13 +62,13 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
|||||||
# PCIE
|
# PCIE
|
||||||
|
|
||||||
set_property PACKAGE_PIN D9 [get_ports {pci_exp_rxp[0]}]
|
set_property PACKAGE_PIN D9 [get_ports {pci_exp_rxp[0]}]
|
||||||
set_property PACKAGE_PIN B10 [get_ports {pci_exp_rxp[1]}]
|
# set_property PACKAGE_PIN B10 [get_ports {pci_exp_rxp[1]}]
|
||||||
set_property PACKAGE_PIN C9 [get_ports {pci_exp_rxn[0]}]
|
set_property PACKAGE_PIN C9 [get_ports {pci_exp_rxn[0]}]
|
||||||
set_property PACKAGE_PIN A10 [get_ports {pci_exp_rxn[1]}]
|
# set_property PACKAGE_PIN A10 [get_ports {pci_exp_rxn[1]}]
|
||||||
set_property PACKAGE_PIN D7 [get_ports {pci_exp_txp[0]}]
|
set_property PACKAGE_PIN D7 [get_ports {pci_exp_txp[0]}]
|
||||||
set_property PACKAGE_PIN B6 [get_ports {pci_exp_txp[1]}]
|
# set_property PACKAGE_PIN B6 [get_ports {pci_exp_txp[1]}]
|
||||||
set_property PACKAGE_PIN C7 [get_ports {pci_exp_txn[0]}]
|
set_property PACKAGE_PIN C7 [get_ports {pci_exp_txn[0]}]
|
||||||
set_property PACKAGE_PIN A6 [get_ports {pci_exp_txn[1]}]
|
# set_property PACKAGE_PIN A6 [get_ports {pci_exp_txn[1]}]
|
||||||
|
|
||||||
set_property PACKAGE_PIN F10 [get_ports {pcie_exp_clkp}]
|
set_property PACKAGE_PIN F10 [get_ports {pcie_exp_clkp}]
|
||||||
set_property PACKAGE_PIN E10 [get_ports {pcie_exp_clkn}]
|
set_property PACKAGE_PIN E10 [get_ports {pcie_exp_clkn}]
|
||||||
|
|||||||
Reference in New Issue
Block a user