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Change pcie clocking

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Byron Lathi
2025-01-26 15:51:19 -08:00
parent 36cba07242
commit c391889a03
7 changed files with 33 additions and 674 deletions
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4
ip/xdma_0/xdma_0.xci
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@@ -14,7 +14,7 @@
"pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
"pl_link_cap_max_link_width": [ { "value": "X2", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"pl_link_cap_max_link_speed": [ { "value": "2.5_GT/s", "resolve_type": "user", "usage": "all" } ],
"ref_clk_freq": [ { "value": "125_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"ref_clk_freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ],
"axi_addr_width": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
@@ -967,7 +967,7 @@
"PCIE_BLK_LOCN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"PL_LINK_CAP_MAX_LINK_WIDTH": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"PL_LINK_CAP_MAX_LINK_SPEED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"REF_CLK_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"REF_CLK_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DRP_CLK_SEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"FREE_RUN_FREQ": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"AXI_ADDR_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],