bslathi19/artix_pcie
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Change pcie clocking

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This commit is contained in:
Byron Lathi
2025-01-26 15:51:19 -08:00
parent 36cba07242
commit c391889a03
7 changed files with 33 additions and 674 deletions
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43
src/artix_pcie.sv
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@@ -1,16 +1,19 @@
module artix_test(
input wire sys_clk_p,
input wire sys_clk_n,
module artix_pcie(
input wire sys_clk_p,
input wire sys_clk_n,
input wire rst_n,
input wire rst_n,
output wire [1 : 0] pci_exp_txp,
output wire [1 : 0] pci_exp_txn,
input wire [1 : 0] pci_exp_rxp,
input wire [1 : 0] pci_exp_rxn
input wire pcie_exp_clkp
input wire pcie_exp_clkn
output wire [1 : 0] pci_exp_txp,
output wire [1 : 0] pci_exp_txn,
input wire [1 : 0] pci_exp_rxp,
input wire [1 : 0] pci_exp_rxn
);
logic clk_200;
logic pcie_refclk;
logic axi_aclk;
logic axi_aresetn;
@@ -26,18 +29,22 @@ logic m_axis_h2c_tvalid_0;
logic m_axis_h2c_tready_0;
logic [7 : 0] m_axis_h2c_tkeep_0;
clk_wiz_0 u_clk_wiz0
(
// Clock out ports
.clk_out1(clk_200), // output clk_out1
// Clock in ports
.clk_in1_p(sys_clk_p), // input clk_in1_p
.clk_in1_n(sys_clk_n) // input clk_in1_n
IBUFDS_GTE2 #(
.CLKRCV_TRST("TRUE"),
.CLKCM_CFG("TRUE"),
.CLKSWING_CFG(2'b11)
) pcie_ibuf (
.I (pcie_exp_clkp),
.IB (pcie_exp_clkn),
.CEB ('0),
.O (pcie_refclk),
.ODIV2 ()
);
xdma_0 u_xdma (
.sys_clk(clk_200),
.sys_rst_n(rst_n),
.sys_clk(pcie_refclk),
.sys_rst_n(rst_n), // this reset is not synchronized. Should it be?
.user_lnk_up(),
.pci_exp_txp(pci_exp_txp),
.pci_exp_txn(pci_exp_txn),

3
src/top.xdc
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@@ -70,5 +70,8 @@ set_property PACKAGE_PIN B6 [get_ports {pci_exp_txp[1]}]
set_property PACKAGE_PIN C7 [get_ports {pci_exp_txn[0]}]
set_property PACKAGE_PIN A6 [get_ports {pci_exp_txn[1]}]
set_property PACKAGE_PIN F10 [get_ports {pcie_exp_clkp}]
set_property PACKAGE_PIN E10 [get_ports {pcie_exp_clkn}]
set_false_path -reset_path -from [get_clocks -of_objects [get_pins u_clk_wiz0/inst/mmcm_adv_inst/CLKOUT0]] -to [get_clocks rgmii_rxc]