bslathi19/artix_pcie
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Move back to gen1x1

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Byron Lathi
2025-01-26 21:17:07 -08:00
parent 3ab2925bf3
commit f6d5002273
1 changed files with 2 additions and 2 deletions
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ip/xdma_0/xdma_0.xci
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@@ -12,8 +12,8 @@
"mode_selection": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ], "mode_selection": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ],
"device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "enabled": false, "usage": "all" } ], "device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ], "pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ],
"pl_link_cap_max_link_width": [ { "value": "X2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "pl_link_cap_max_link_width": [ { "value": "X1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"pl_link_cap_max_link_speed": [ { "value": "5.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "pl_link_cap_max_link_speed": [ { "value": "2.5_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"ref_clk_freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "ref_clk_freq": [ { "value": "100_MHz", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ], "drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ],
"free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ], "free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ],